Electronic component comprising substrate with thermal indicator

Patent metadata

Field	Value
Publication number	US-11469153-B2
Application number	US-201916672501-A
Country	US
Kind code	B2
Filing date	Nov 3, 2019
Priority date	Sep 12, 2019
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

An electronic component includes a substrate comprising a die attach region and a perimeter region on a front side of the substrate; and at least one thermal indicator disposed within the perimeter region for monitoring the cumulative heat exposure of the substrate. The thermal indicator signals when the predetermined thermal budget limit that correlates with the decline in the condition of the OSP layer or the degradation of the adhesion of the die attach films is reached.

First claim

What is claimed is:

1. An electronic component, comprising:
a substrate comprising a die attach region and a perimeter region on a front side of the substrate, wherein the die attach region further comprises an array of sub-regions;
a trench recessed into the front side of the substrate within the perimeter region; and
at least one thermal indicator disposed within the trench for monitoring the cumulative heat exposure of the substrate, wherein the thermal indicator comprises a base material having a porous structure and a heat-sensing agent, and wherein the base material is soaked with the heat-sensing agent and the base material is fixed to interior surface of the trench.

2. The electronic component according to claim 1 , wherein the substrate comprises a package substrate, a wiring board, or a printed circuit board.

3. The electronic component according to claim 1 , wherein the substrate comprise a reinforced polymer laminate or a polyimide resin.

4. The electronic component according to claim 1 , wherein the substrate further comprises a plurality of pin holes for positioning purpose, which is disposed in the perimeter region.

5. The electronic component according to claim 1 , further comprising:
an integrated circuit (IC) die adhesively bonded in each of the sub-regions using a die attach film.

6. The electronic component according to claim 5 , wherein gold-plated fingers are provided along edges of the IC die in each of the sub-regions.

7. The electronic component according to claim 1 further comprising:
copper-plated solder ball pads provided on a rear side of the substrate.

8. The electronic component according to claim 7 , wherein the heat-sensing agent comprises azole compounds, such as imidazoles, benzimidazoles and their derivatives.

9. The electronic component according to claim 1 further comprising:
an organic solderability preservative (OSP) layer disposed on a surface of each of the copper-plated solder ball pads, wherein the at least one thermal indicator signals when a thermal budget limit that correlates with decline in the condition of the SOP layer or degradation of adhesion of the die attach film is reached.

10. The electronic component according to claim 1 , wherein the heat-sensing agent has an evaporation temperature that is approximately equal to that of the OSP layer.

11. The electronic component according to claim 1 , wherein the heat-sensing agent is supported by the base material in the trench and is coupled to the base material with a bonding mechanism.

12. The electronic component according to claim 1 , wherein the heat-sensing agent comprises diacetylenic compound and solvent.

13. The electronic component according to claim 12 , wherein the heat-sensing agent further comprises dye fragments, pigments, or colorants.

14. The electronic component according to claim 1 , wherein the heat-sensing agent further comprises a binder.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Chen Peng
• Zhou Houde
• Gu Chao

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title