Vector table load instruction with address generation field to access table offset value

Patent metadata

Field	Value
Publication number	US-11468003-B2
Application number	US-202017026412-A
Country	US
Kind code	B2
Filing date	Sep 21, 2020
Priority date	Jul 14, 2011
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.

First claim

What is claimed is:

1. A device comprising:
a vector core configured to couple to a memory, wherein the vector core includes:
a set of address generators; and
a table lookup unit configured to:
receive an instruction to retrieve a set of table values from a set of tables stored in the memory, wherein the instruction includes a first field that specifies a first address generator of the set of address generators that stores a table offset associated with a first table of the set of tables; and
in response to the instruction, read the set of table values from the memory.

2. The device of claim 1 , wherein the instruction includes a second field that specifies a number of the set of tables from which the set of table values are to be read.

3. The device of claim 1 , wherein the instruction includes a second field that specifies a number of table values to be read from each table of the set of tables.

4. The device of claim 1 , wherein the instruction includes a second field that specifies an offset of a first table value of the set of table values into the first table.

5. The device of claim 1 , wherein the table lookup unit is configured to read the set of table values from the set of tables in parallel.

6. The device of claim 1 , wherein the table lookup unit is configured to:
read the set of table values from a first set of locations in the memory; and
store the set of table values in a second set of locations in the memory that is different from the first set of locations.

7. The device of claim 1 , wherein:
the instruction includes a second field that specifies a vector register; and
the table lookup unit is configured to store the set of table values in the vector register in response to the instruction.

8. The device of claim 1 , wherein:
the memory includes a set of banks;
each table of the set of tables is to be stored in a respective bank of the set of banks; and
the table lookup unit is configured to read each value of the set of table values from a different bank of the set of banks.

9. The device of claim 1 further comprising:
a scalar core coupled to the vector core, wherein the scalar core is configured to:
receive a set of instructions that includes a set of scalar instructions and a set of vector instructions;
perform the set of scalar instructions; and
provide the set of vector instructions to the vector core.

10. The device of claim 1 further comprising the memory.

11. A processor comprising:
a memory configured to store a set of tables; and
a vector coprocessor core coupled to the memory, wherein the vector coprocessor core includes:
a set of address generators; and
a table lookup unit configured to execute a table lookup loop to retrieve a set of table values from the set of tables stored in the memory, wherein the table lookup loop includes an instruction that includes a first field that specifies a first address generator of the set of address generators that stores a table offset associated with a first table of the set of tables.

12. The processor of claim 11 , wherein the instruction includes a second field that specifies a number of the set of tables from which the set of table values are to be read.

13. The processor of claim 11 , wherein the instruction includes a second field that specifies a number of table values to be read from each table of the set of tables.

14. The processor of claim 11 , wherein the instruction includes a second field that specifies an offset of a first table value of the set of table values into the first table.

15. The processor of claim 11 , wherein the table lookup unit is configured to read the set of table values from the set of tables in parallel.

16. The processor of claim 11 , wherein the table lookup unit is configured to:
read the set of table values from a first set of locations in the memory; and
store the set of table values in a second set of locations in the memory that is different from the first set of locations.

17. The processor of claim 11 , wherein:
the processor further comprises a vector register;
the instruction includes a second field that specifies the vector register; and
the table lookup unit is configured to store the set of table values in the vector register in response to the instruction.

18. The processor of claim 11 , wherein:
the memory includes a set of banks;
the memory is configured to store each table of the set of tables in a respective bank of the set of banks; and
the table lookup unit is configured to read each value of the set of table values from a different bank of the set of banks.

19. The processor of claim 11 further comprising:
a scalar core coupled to the vector coprocessor core, wherein the scalar core is configured to:
receive a set of instructions that includes a set of scalar instructions and a set of vector instructions;
perform the set of scalar instructions; and
provide the set of vector instructions to the vector coprocessor core.

20. The processor of claim 11 , wherein:
the vector coprocessor core includes a set of execution units coupled in parallel in lanes;
the instruction includes a second field that specifies at least one of: a number of the set of tables from which the set of table values are to be read or a number of table values to be read from each table of the set of tables; and
a limit on the second field depends on a number of the lanes of the vector coprocessor core.

Assignees

• Texas Instruments Inc

Inventors

• Hung Ching-Yu
• Inamori Shinri
• Sankaran Jagadeesh
• Chang Peter

Classifications

• G06F9/345

  of multiple operands or results {(addressing multiple banks G06F12/06)} · CPC title

• G06F9/3013

  according to data content, e.g. floating-point registers, address registers · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30098

  Register arrangements · CPC title