Accelerating table lookups using a decoupled lookup table accelerator in a system on a chip
US-12572387-B2 · Mar 10, 2026 · US
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Hung Ching-Yu patents
Hung Ching-Yu is listed as an inventor on 51 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Hung Ching-Yu |
| Total patents | 51 |
| First publication | Jul 28, 2015 |
| Latest publication | Mar 10, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Architecture for reuse of frame data across multi-dimensional data processors
US-2026051161-A1 · Feb 19, 2026 · US
Image data sampling architecture for image feature tracking
US-2026051162-A1 · Feb 19, 2026 · US
Architecture and instruction set for multi-dimensional data processing
US-2026051160-A1 · Feb 19, 2026 · US
Parallelized architecture for multi-dimensional data processors
US-2026051013-A1 · Feb 19, 2026 · US
Processing data using accelerators in a system on a chip
US-2026037330-A1 · Feb 5, 2026 · US
Load and store memory architecture
US-2026037457-A1 · Feb 5, 2026 · US
Coordinating processing tasks between one-dimensional processing engines and two-dimensional processing engines
US-2026038079-A1 · Feb 5, 2026 · US
Computer architecture to validate image frame and image line data in a single pass
US-2026037264-A1 · Feb 5, 2026 · US
Systems and methods for performing inter-accelerator data transfers
US-2026037480-A1 · Feb 5, 2026 · US
Recent patents
Latest publications not already listed above.
Systems and methods for performing direct memory access data transfers
US-2026037478-A1 · Feb 5, 2026 · US
Using a hardware sequencer in a direct memory access system of a system on a chip
US-2025103529-A1 · Mar 27, 2025 · US
Using a hardware sequencer in a direct memory access system of a system on a chip
US-12204475-B2 · Jan 21, 2025 · US
Performing load and permute with a single instruction in a system on a chip
US-12118353-B2 · Oct 15, 2024 · US
Performing load and store operations of 2D arrays in a single cycle in a system on a chip
US-12099439-B2 · Sep 24, 2024 · US
Using per memory bank load caches for reducing power use in a system on a chip
US-12093539-B2 · Sep 17, 2024 · US
Built-in self-test for a programmable vision accelerator of a system on a chip
US-12050548-B2 · Jul 30, 2024 · US
Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chip
US-2024134645-A1 · Apr 25, 2024 · US
Reduced memory write requirements in a system on a chip using automatic store predication
US-11954496-B2 · Apr 9, 2024 · US
Hardware accelerated anomaly detection using a min/max collector in a system on a chip
US-11940947-B2 · Mar 26, 2024 · US
Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chip
US-11934829-B2 · Mar 19, 2024 · US
Accelerating table lookups using a decoupled lookup table accelerator in a system on a chip
US-2024045722-A1 · Feb 8, 2024 · US
Accelerating table lookups using a decoupled lookup table accelerator in a system on a chip
US-11836527-B2 · Dec 5, 2023 · US
Performing multiple point table lookups in a single cycle in a system on chip
US-11704067-B2 · Jul 18, 2023 · US
Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chip
US-2023185569-A1 · Jun 15, 2023 · US
Built-in self-test for a programmable vision accelerator of a system on a chip
US-2023125397-A1 · Apr 27, 2023 · US
Hardware accelerated anomaly detection using a min/max collector in a system on a chip
US-11636063-B2 · Apr 25, 2023 · US
Using per memory bank load caches for reducing power use in a system on a chip
US-2023124604-A1 · Apr 20, 2023 · US
Using a hardware sequencer in a direct memory access system of a system on a chip
US-2023111014-A1 · Apr 13, 2023 · US
Performing load and permute with a single instruction in a system on a chip
US-2023076599-A1 · Mar 9, 2023 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Nvidia Corp | 45 |
| Texas Instruments Inc | 6 |
| Inamori Shinri | 2 |
| Sankaran Jagadeesh | 2 |
| Chang Peter | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/30036 | 23 |
| G06F9/30043 | 23 |
| G06F13/28 | 21 |
| G06F9/3001 | 20 |
| G06F15/8053 | 19 |