Methods of fabricating capacitor and semiconductor device and semiconductor devices and apparatus including the same

Patent metadata

Field	Value
Publication number	US-11462610-B2
Application number	US-202016947090-A
Country	US
Kind code	B2
Filing date	Jul 17, 2020
Priority date	Jul 30, 2019
Publication date	Oct 4, 2022
Grant date	Oct 4, 2022

Abstract

Capacitor forming methods may include sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate, forming a mask pattern on the second mold layer, forming a recess in the second mold layer, the first support material layer, and the first mold layer using the mask pattern as a mask, forming a lower electrode in the recess, removing the mask pattern by a dry cleaning process, reducing a width of an upper portion of the lower electrode, removing the first mold layer, forming a dielectric layer on a surface of the lower electrode, and forming an upper electrode on the dielectric layer.

First claim

What is claimed is:

1. A capacitor forming method comprising:
sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate;
forming a mask pattern on the second mold layer;
forming a recess in the second mold layer, the first support material layer, and the first mold layer using the mask pattern as a mask;
forming a lower electrode in the recess; removing the mask pattern by a dry cleaning process; reducing a width of an upper portion of the lower electrode;
removing the first mold layer; forming a dielectric layer on a surface of the lower electrode; and
forming an upper electrode on the dielectric layer,
wherein the method further comprises removing a portion of the second mold layer, before the reducing of the width of the upper portion of the lower electrode and after the removing of the mask pattern.

2. The capacitor forming method of claim 1 , further comprising, before the removing of the first mold layer, forming a second support material layer.

3. The capacitor forming method of claim 2 , further comprising forming a third mold layer on the first support material layer, after the reducing of the width of the upper portion of the lower electrode and before the forming of the second support material layer.

4. The capacitor forming method of claim 3 , wherein the second support material layer is formed on the third mold layer.

5. The capacitor forming method of claim 4 , further comprising removing a portion of the third mold layer to expose the upper portion of the lower electrode, before the forming of the second support material layer.

6. The capacitor forming method of claim 5 , wherein
the second support material layer is formed to cover an upper surface of the lower electrode and a portion of a side surface of the upper portion of the lower electrode.

7. The capacitor forming method of claim 5 , wherein
the second support material layer is formed to expose an upper surface of the lower electrode and to cover a portion of a side surface of the upper portion of the lower electrode.

8. The capacitor forming method of claim 1 , wherein
the dry cleaning process is a plasma cleaning process in which no electrical biases are applied.

9. The capacitor forming method of claim 1 , wherein
after the reducing of the width of the upper portion of the lower electrode, an upper end of the lower electrode has a width in a range of about 60% to about 90% of a width of a lower portion of the lower electrode.

10. A method of fabricating a semiconductor device, the method comprising:
sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate;
forming a mask pattern on the second mold layer;
forming a recess in the first mold layer, the first support material layer, and the second mold layer by patterning the first mold layer, the first support material layer, and the second mold layer using the mask pattern as a mask;
forming a lower electrode in the recess; removing the mask pattern by a dry cleaning process to expose an upper portion of the lower electrode;
reducing a width of the upper portion of the lower electrode;
removing the first mold layer; forming a dielectric layer on a surface of the lower electrode; and
forming an upper electrode on the dielectric layer,
wherein the method further comprises removing a portion of the second mold layer, after the removing of the mask pattern and before the reducing of the width of the upper portion of the lower electrode.

11. The method of claim 10 , wherein
the lower electrode has a cylindrical shape.

12. The method of claim 10 , wherein after the reducing of the width of the upper portion of the lower electrode, an upper end of the lower electrode has a width in a range of about 60% to about 90% of a width of a lower portion of the lower electrode.

13. The method of claim 10 , wherein
the reducing of the width of the upper portion of the lower electrode is performed by wet etching.

14. The method of claim 10 , wherein
an upper surface of the lower electrode is coplanar with an upper surface of the mask pattern.

15. A method of fabricating a semiconductor device, the method comprising:
forming a transistor comprising a gate structure and an impurity area on a substrate;
forming, on the substrate, an interlayer insulating layer that covers the transistor and comprises a contact plug electrically connected to the impurity area;
sequentially forming a first mold layer, a first support material layer, and a second mold layer on the interlayer insulating layer; forming a mask pattern on the second mold layer;
forming a recess in the first mold layer, the first support material layer, and the second mold layer using the mask pattern as a mask;
forming a lower electrode material layer on an upper surface of the mask pattern and in the recess;
forming a lower electrode by removing a portion of the lower electrode material layer until the upper surface of the mask pattern is exposed;
removing the mask pattern by a dry cleaning process;
reducing a width of an upper portion of the lower electrode; removing the first mold layer;
forming a dielectric layer on a surface of the lower electrode; and
forming an upper electrode on the dielectric layer,
wherein the method further comprises removing a portion of the second mold layer, after the removing of the mask pattern and before the reducing of the width of the upper portion of the lower electrode.

16. The method of claim 10 , wherein removing the mask pattern exposes an entirety of a side surface of the upper portion of the lower electrode, and
wherein reducing the width of the upper portion of the lower electrode comprises etching the side surface of the upper portion of the lower electrode by performing an isotropic etching process.

17. The method of claim 10 , further comprising, before sequentially forming the first mold layer, the first support material layer, and the second mold layer:
forming a transistor comprising a gate structure and an impurity area on the substrate; and
forming an interlayer insulating layer extending on the transistor and comprising a contact plug electrically connected to the impurity area.

18. The method of claim 10 , wherein removing the portion of the second mold layer comprises removing the second mold layer until an upper surface of the first support material layer is exposed, and the upper portion of the lower electrode protrudes above the upper surface of the first support material layer after removing the portion of the second mold layer, and wherein reducing the width of the upper portion of the lower electrode comprises etching a side surface of the upper portion of the lower electrode by performing an isotropic etching process.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Yoonyoung
• Lee Byunghyun
• Ku Byeongjoo
• Kim Seungjin
• Park Sangjae
• Bae Jinwoo
• Lee Hangeol
• Choi Bowo
• Hong Hyunsil

Classifications

• H01L28/91

  Electricity · mapped topic

• H01L28/92 Primary

  Electricity · mapped topic

• H01L28/56

  Electricity · mapped topic

• H10D1/684

  the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers · CPC title

• H10D1/042

  using deposition processes to form electrode extensions · CPC title