Power management integrated circuit including detection circuit with capacitive element

Patent metadata

Field	Value
Publication number	US-11460873-B2
Application number	US-202117338336-A
Country	US
Kind code	B2
Filing date	Jun 3, 2021
Priority date	Jun 9, 2020
Publication date	Oct 4, 2022
Grant date	Oct 4, 2022

Abstract

A power management integrated circuit (PMIC) includes; a DC-DC converter configured to provide output power to a load, a controller configured to control switching of the DC-DC converter, and a sense circuit including a capacitive element and configured to detect an output current flowing through a node between the DC-DC converter and the load.

First claim

What is claimed is:

1. A power management integrated circuit (PMIC), comprising:
a DC-DC converter configured to provide output power to a load;
a controller configured to control switching of the DC-DC converter; and
a sense circuit including a capacitive element and configured to detect an output current flowing through a node between the DC-DC converter and the load,
wherein the sense circuit further includes an operational amplifier and at least one resistor,
the capacitive element is connected between a negative input terminal of the operational amplifier and ground, and
the PMIC adjusts capacitance of the capacitive element in response to operating frequency driving the PMIC and forms an additional pole and zero in relation to the capacitive element of the sense circuit.

2. The PMIC of claim 1 , wherein the at least one resistor comprises a first resistor connected to ground, and a second resistor connected to the node, and the first and second resistors are connected to a positive input terminal of the operational amplifier, and
the at least one resistor further comprises a third resistor connected to an output terminal of the operational amplifier, and a fourth resistor connected to ground, and the third and fourth resistors are connected to the negative input terminal.

3. The PMIC of claim 2 , wherein a ratio of resistance values for the first resistor and the second resistor is the same as a ratio of resistance values for the third resistor and the fourth resistor.

4. The PMIC of claim 1 , wherein the DC-DC converter includes a buck converter.

5. The PMIC of claim 1 , wherein the DC-DC converter includes a boost converter.

6. The PMIC of claim 1 , wherein the DC-DC converter includes a buck-boost converter.

7. The PMIC of claim 1 , wherein the DC-DC converter includes a linear regulator.

8. The PMIC of claim 1 , wherein the DC-DC converter has an operating bandwidth and phase margin determined at least in part by the capacitive element of the sense circuit.

9. A power management integrated circuit (PMIC), comprising:
a DC-DC converter configured to provide output power to a load;
a controller configured to control switching of the DC-DC converter;
a sense circuit including a capacitive array and configured to detect an output current flowing through a node between the DC-DC converter and the load; and
a frequency-digital converter configured to adjust a total capacitance of the capacitive array.

10. The PMIC of claim 9 , wherein the frequency-digital converter adjusts the total capacitance by switching the capacitive array in response to an operating frequency received from the controller.

11. The PMIC of claim 9 , wherein the DC-DC converter includes an inductor, and
the frequency-digital converter converts an inductor current flowing through the inductor into a digital code.

12. The PMIC of claim 9 , wherein the sense circuit further includes an operational amplifier and at least one resistor, and
the capacitive array is connected between a negative input terminal of the operational amplifier and ground.

13. The PMIC of claim 12 , wherein the at least one resistor comprises a first resistor connected to ground, and a second resistor connected to the node, and the first and second resistors are connected to a positive input terminal of the operational amplifier, and
the at least one resistor further comprises a third resistor connected to an output terminal of the operational amplifier, and a fourth resistor connected to ground, and the third and fourth resistors are connected to the negative input terminal of the operational amplifier.

14. The PMIC of claim 13 , wherein a ratio of resistance values for the first resistor and the second resistor is the same as a ratio of resistance values for the third resistor and the fourth resistor.

15. The PMIC of claim 9 , wherein the PMIC forms an additional pole and zero in relation to the capacitive array of the sense circuit.

16. An operating method for a power management integrated circuit (PMIC), the method comprising:
detecting a change in an output current at a node between the PMIC and a load;
supplying an output voltage corresponding to the output current to the node in accordance with a zero and a pole added in relation to a capacitive element included in a sense circuit; and
adjusting capacitance of the capacitive element in response to an operating frequency driving the PMIC,
wherein the adjusting of capacitance of the capacitive element comprises
measuring an inductor current flowing through an inductor in the PMIC, and
adjusting the capacitance in response to a frequency of the inductor current.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Nam Hyunseok
• Kong Jeongwoon
• Bae Junhyun
• Lee Sangyoung

Classifications

• H02J7/855

  with circuits adapted for supplying loads from the battery · CPC title

• H02M3/157

  with digital control · CPC title

• H02J2207/20

  Charging or discharging characterised by the power electronics converter · CPC title

• H02M3/1582

  Buck-boost converters (H02M3/1584 takes precedence) · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title