Loop compensation using differential difference amplifier for negative feedback circuits

Patent metadata

Field	Value
Publication number	US-10056871-B2
Application number	US-201715473538-A
Country	US
Kind code	B2
Filing date	Mar 29, 2017
Priority date	Nov 4, 2016
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

A loop compensation circuit includes a differential difference amplifier having a first transconductance stage with a first input terminal and a second input terminal. The first input terminal is coupled to a voltage reference and the second input terminal is coupled to a feedback node. The amplifier also includes a second transconductance stage having a third input terminal and a fourth input terminal. The third input terminal is coupled to a virtually specified fixed voltage and the fourth input terminal is coupled to a fixed specified voltage. The loop compensation circuit also includes a feedback impedance coupled between an output of the differential difference amplifier and the third input terminal and a second impedance between the third input terminal and the fixed specified voltage.

First claim

What is claimed is:

1. A loop compensation circuit, comprising:
a differential difference amplifier, in a negative feedback loop, having:
a first transconductance stage with a first input terminal and a second input terminal, the first input terminal coupled to a voltage reference and the second input terminal coupled to a feedback node configured to receive a feedback voltage from an output of a switching power circuit; and
a second transconductance stage having a third input terminal and a fourth input terminal, the fourth input terminal coupled to a fixed specified voltage;

a feedback impedance coupled between an output of the differential difference amplifier and the third input terminal, the output of the differential difference amplifier comprising a control signal configured to control the switching power circuit, which is configured to receive an input voltage and generate an output voltage at the output of the switching power circuit to drive a load; and
a second impedance between the third input terminal and the fixed specified voltage.

2. The loop compensation circuit of claim 1 , in which the feedback impedance comprises a resistor in series with either a metal oxide semiconductor capacitor (MOSCAP) or a metal-insulator-metal capacitor (MIMCAP).

3. The loop compensation circuit of claim 1 , in which the fixed specified voltage comprises a ground.

4. The loop compensation circuit of claim 1 , in which the third input terminal is coupled to a virtually specified fixed voltage.

5. The loop compensation circuit of claim 4 , in which the virtually specified fixed voltage comprises a virtual ground.

6. The loop compensation circuit of claim 5 , in which the virtual ground for a metal oxide semiconductor capacitor (MOSCAP) comprises a common mode voltage of a feedback path of the loop compensation circuit shifted down to ground while the voltage reference and a feedback voltage at the feedback node are maintained in a specified programmable range.

7. The loop compensation circuit of claim 1 , in which the first input terminal and the third input terminal are positive input terminals, and the second input terminal and the fourth input terminal are negative input terminals.

8. A loop compensation method, comprising:
controlling an output voltage of a differential difference amplifier based at least in part on a ratio of a first transconductance of a first transconductance stage of the differential difference amplifier and a second transconductance of a second transconductance stage of the differential difference amplifier, the first transconductance stage having a first pair of inputs and the second transconductance stage having a second pair of inputs, in which a second input of the second pair of inputs is coupled to a fixed specified voltage;
receiving, at a first input of the first pair of inputs, a feedback voltage from an output of a switching power circuit to control the output voltage of the difference amplifier in accordance with a negative feedback loop, the switching power circuit configured to receive an input voltage and to generate an output voltage at the output of the switching power circuit to drive a load; and
feeding back the output voltage of the difference amplifier to a first input of the second pair of inputs corresponding to the second transconductance stage.

9. The loop compensation method of claim 8 , further comprising feeding back the output voltage to the first input of the second pair of inputs via a resistor in series with either a metal oxide semiconductor capacitor (MOSCAP) or a metal-insulator-metal capacitor (MIMCAP).

10. The loop compensation method of claim 8 , further comprising receiving a reference voltage at a second input of the first pair of inputs corresponding to the first transconductance stage of the differential difference amplifier.

11. The loop compensation method of claim 10 , in which the output voltage is based at least in part on a difference between the reference voltage and the feedback voltage.

12. The loop compensation method of claim 10 , further comprising shifting an input common-mode voltage down to ground in a feedback path of a loop compensation circuit including the differential difference amplifier while maintaining the reference voltage and the feedback voltage in a specified programmable range.

13. The loop compensation method of claim 8 , further comprising receiving a fixed specified voltage at a second input of the second pair of inputs.

14. The loop compensation method of claim 8 , further comprising adjusting a closed loop gain of the differential difference amplifier by adjusting the ratio.

15. The loop compensation method of claim 8 , in which feeding back the output voltage comprises feeding back the voltage to the first input of the second pair of inputs corresponding to the second transconductance stage via a virtually specified fixed voltage terminal.

16. A loop compensation circuit, comprising:
a differential difference amplifier, in a negative feedback loop, having:
a first transconductance stage with a first input terminal and a second input terminal, the first input terminal coupled to a voltage reference and the second input terminal coupled to a feedback node configured to receive a feedback voltage from an output of a switching power circuit; and
a second transconductance stage having a third input terminal and a fourth input terminal, the fourth input terminal coupled to a fixed specified voltage;

means for generating impedance, the impedance generating means coupled between an output of the differential difference amplifier and the third input terminal, the output of the differential difference amplifier comprising a control signal configured to control the switching power circuit, which is configured to receive an input voltage and generate an output voltage at the output of the switching power circuit to drive a load; and
a second impedance between the third input terminal and the fixed specified voltage.

17. The loop compensation circuit of claim 16 , in which the fixed specified voltage comprises a ground.

18. The loop compensation circuit of claim 16 , in which the third input terminal is coupled to a virtually specified fixed voltage.

19. The loop compensation circuit of claim 18 , in which the impedance generating means is coupled to a terminal having the virtually specified fixed voltage.

20. The loop compensation circuit of claim 18 , in which the virtually specified fixed voltage comprises a virtual ground.

21. The loop compensation circuit of claim 20 , in which the virtual ground comprises a common mode voltage of a feedback path of the loop compensation circuit shifted down to ground while the voltage reference and a feedback voltage at the feedback node are maintained in a specified programmable range.

Assignees

• Qualcomm Inc

Inventors

• Kwak Taewoo
• Rutkowski Joseph

Classifications

• H03F3/45071

  with semiconductor devices only · CPC title

• H03F2203/45116

  Feedback coupled to the input of the differential amplifier · CPC title

• H03F2203/45526

  the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC · CPC title

• H03F1/0233

  by using a signal derived from the output signal, e.g. bootstrapping the voltage supply · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title