Wafer scale ultrasonic sensor assembly and method for manufacturing the same

US11460341B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11460341-B2
Application numberUS-201916429801-A
CountryUS
Kind codeB2
Filing dateJun 3, 2019
Priority dateDec 14, 2018
Publication dateOct 4, 2022
Grant dateOct 4, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

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A wafer scale ultrasonic sensor assembly includes a wafer substrate, an ultrasonic element, first and second protective layers, conductive wires, a transmitting material, an ASIC, a conductive bump, and a soldering portion. The wafer substrate includes a via. The ultrasonic element is exposed to the via. The conductive wires are on the first protective layer and connected to the ultrasonic element. The second protective layer covers the conductive wires, and the second protective layer has an opening corresponding to the ultrasonic element. The transmitting material contacts the ultrasonic element. The ASIC is connected to the wafer substrate, so that the via forms a space between the ASIC and the ultrasonic element. The conductive pillar is in a via defined through the ASIC, the wafer substrate, and the first protective layer, and the conducive pillar is respectively connected to the conductive wires and the soldering portion.

First claim

Opening claim text (preview).

What is claimed is: 1. A wafer scale ultrasonic sensor assembly, comprising: a wafer substrate comprising a through groove penetrated through a first surface of the wafer substrate and a second surface of the wafer substrate, wherein the first surface is opposite to the second surface; an ultrasonic element on the first surface of the wafer substrate, wherein the ultrasonic element has an upper surface and a lower surface, and the lower surface of the ultrasonic element is exposed from the through groove; a first protection layer on the first surface of the wafer substrate and surrounding the ultrasonic element; a first conductive wire and a second conductive wire on the first protection layer and respectively connected to the upper surface of the ultrasonic element; a second protection layer covering the first conductive wire and the second conductive wire, wherein the second protection layer has an opening, and the upper surface of the ultrasonic element corresponds to the opening; a transmitting material in the opening and contacting the upper surface of the ultrasonic element; an application-specific integrated circuit chip (ASIC) comprising a connection surface and a bottom surface opposite to the connection surface, wherein the connection surface is connected to the second surface of the wafer substrate, and the through groove forms a space between the connection surface of the ASIC and the lower surface of the ultrasonic element; a conductive pillar in a via defined through the ASIC, the wafer substrate, and the first protection layer, wherein the conductive pillar is connected to the first conductive wire or the second conductive wire; and a soldering portion on the bottom surface of the ASIC, wherein the soldering portion is connected to the conductive pillar. 2. The wafer scale ultrasonic sensor assembly according to claim 1 , wherein the connection surface of the ASIC and the second surface of the wafer substrate are connected with each other directly through anodizing. 3. The wafer scale ultrasonic sensor assembly according to claim 1 , wherein the ultrasonic element comprises a first piezoelectric layer, a first electrode, a second piezoelectric layer, and a second electrode stacked on the wafer substrate sequentially, wherein the second electrode does not cover portions of an upper surface of the first electrode, the transmitting material contacts the second electrode, the first electrode is connected to the first conductive wire, and the second electrode is connected to the second conductive wire. 4. The wafer scale ultrasonic sensor assembly according to claim 3 , wherein the ASIC further comprises a plurality of connection pads on the connection surface of the ASIC. 5. The wafer scale ultrasonic sensor assembly according to claim 4 , wherein the via is defined through one of the connection pads connected to the conductive pillar. 6. The wafer scale ultrasonic sensor assembly according to claim 1 , wherein the ultrasonic element comprises a first ultrasonic unit and a second ultrasonic unit, wherein the first ultrasonic unit comprises a first piezoelectric layer and a first electrode; the first piezoelectric layer is on the wafer substrate, and the first piezoelectric layer and the first protection layer have a first contact hole, so that the first piezoelectric layer communicates with the first protection layer through the first contact hole; the first electrode is enclosed by the first piezoelectric layer, and a portion of the first conductive wire is in the first contact hole and connected to the first electrode; wherein the second ultrasonic unit is not overlapped with the first ultrasonic unit in a direction perpendicular to the first surface of the wafer substrate; the second ultrasonic unit comprises a second piezoelectric layer, a second circuit pattern layer, and a second electrode; the second piezoelectric layer is on the wafer substrate, and the first piezoelectric layer and the second piezoelectric layer are the same layer and separated from each other; the second circuit pattern layer is enclosed by the second piezoelectric layer, the second circuit pattern layer and the first electrode are the same layer and separated from each other, and the second electrode is on the second piezoelectric layer; the first protection layer has a second contact hole communicating with the opening, a portion of the second conductive wire is in the second contact hole and connected to the second electrode, and a portion of the transmitting material is in the second contact hole and contacting the second electrode. 7. The wafer scale ultrasonic sensor assembly according to claim 6 , wherein the ASIC further comprises a plurality of connection pads on the connection surface of the ASIC. 8. The wafer scale ultrasonic sensor assembly according to claim 7 , wherein the via is defined through one of the connection pads connected to the conductive pillar. 9. The wafer scale ultrasonic sensor assembly according to claim 1 , wherein the transmitting material is polydimethylsiloxane. 10. A method for manufacturing wafer scale ultrasonic sensor assembly, comprising: an ultrasonic element forming step: forming an ultrasonic element on a first surface of a wafer substrate, wherein the ultrasonic element comprises a first electrode and a second electrode not connected to the first electrode; a first protection layer forming step: forming a first protection layer on an upper surface of the ultrasonic element and the first surface of the wafer substrate, wherein the first protection layer has a first contact hole and a second contact hole, a portion of the first electrode is exposed from the first contact hole, and a portion of the second electrode is exposed from the second contact hole; a wire connecting step: forming a first conductive wire and a second conductive wire, wherein the first conductive wire and the second conductive wire are on the first protection layer, portions of the first conductive wire are in the first contact hole and connected to the first electrode of the ultrasonic element, and portions of the second conductive wire are in the second contact hole and connected to the second electrode of the ultrasonic element; a second protection layer forming step: forming a second protection layer to cover the first conductive wire and the second conductive wire; an opening forming step: forming an opening on the second protection layer, wherein the opening at least exposes a portion of the second electrode; a removing step: removing a portion of the wafer substrate to form a through groove defined through the first surface and a second surface of the wafer substrate, wherein a lower surface of the ultrasonic element is exposed from the through groove, and the second surface is opposite to the first surface; a connecting step: connecting a connection surface of an ASIC and the second surface of the wafer substrate through anodizing, so that the through groove has a space between the connection surface and the lower surface of the ultrasonic element; a via forming step: forming a via defined through the ASIC, the wafer substrate, and the first protection layer; a via filling step: filling a conductive material in the via to form a conductive pillar, wherein the conductive pillar is connected to the first conductive wire or the second conductive wire; a soldering portion forming step: forming a soldering portion on a bottom surface of the ASIC, wherein a position of the soldering portion corresponds to a position of the conductive pillar, and the soldering portion is connected to the conductive pillar; and a transmitting material filling step: filling a transmitting material in the opening, wherein the tran

Assignees

Inventors

Classifications

  • B06B1/0622Primary

    on one surface · CPC title

  • non-optical, e.g. ultrasonic or capacitive sensing · CPC title

  • Specific application · CPC title

  • Methods or apparatus specially adapted for transmitting mechanical vibrations of infrasonic, sonic, or ultrasonic frequency · CPC title

  • Driving circuits (specially adapted for particular applications, see the relevant subclass, e.g. G01; circuits for steering transducer arrays G10K11/34; basic circuits H03) · CPC title

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What does patent US11460341B2 cover?
A wafer scale ultrasonic sensor assembly includes a wafer substrate, an ultrasonic element, first and second protective layers, conductive wires, a transmitting material, an ASIC, a conductive bump, and a soldering portion. The wafer substrate includes a via. The ultrasonic element is exposed to the via. The conductive wires are on the first protective layer and connected to the ultrasonic elem…
Who is the assignee on this patent?
J Metrics Tech Co Ltd, Univ Peking Shenzhen Graduate School
What technology area does this patent fall under?
Primary CPC classification B06B1/0622. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Oct 04 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).