Nonvolatile memory device with a metal-insulator-metal (MIM) capacitor in a substrate and integration schemes

Patent metadata

Field	Value
Publication number	US-11456306-B2
Application number	US-202017100954-A
Country	US
Kind code	B2
Filing date	Nov 23, 2020
Priority date	Nov 23, 2020
Publication date	Sep 27, 2022
Grant date	Sep 27, 2022

Abstract

A nonvolatile memory device is provided. The nonvolatile memory device comprises a floating gate arranged over a first active region, whereby the first active region is in an active layer of a substrate. A metal-insulator-metal (MIM) capacitor may be provided laterally adjacent to the floating gate, whereby a portion of the metal-insulator-metal capacitor is in the active layer. A contact pillar may connect a first electrode of the metal-insulator-metal capacitor to the floating gate.

First claim

What is claimed:

1. A nonvolatile memory device comprising:
a floating gate over a first active region, wherein the first active region is in an active layer of a substrate;
a metal-insulator-metal (MIM) capacitor laterally adjacent to the floating gate, wherein a portion of the metal-insulator-metal capacitor is in the active layer; and
a contact pillar connecting a first electrode of the metal-insulator-metal capacitor to the floating gate.

2. The nonvolatile memory device of claim 1 , wherein the substrate comprises a first dielectric layer under the active layer, and a lower portion of the metal-insulator-metal capacitor extends vertically to the first dielectric layer.

3. The nonvolatile memory device of claim 2 , wherein the lower portion of the metal-insulator-metal capacitor extends into an upper portion of the first dielectric layer in the substrate.

4. The nonvolatile memory device of claim 1 , wherein an upper portion of the metal-insulator-metal capacitor extends vertically in an inter layer dielectric (ILD) layer above the substrate.

5. The nonvolatile memory device of claim 4 , wherein the upper portion of the metal-insulator-metal capacitor further comprises:
an extension portion extending laterally in an inter metal (IMD) dielectric layer above the inter layer dielectric layer.

6. The nonvolatile memory device of claim 5 , wherein the extension portion at least partially overlaps laterally with the floating gate.

7. The nonvolatile memory device of claim 1 further comprising:
a first isolation region in the substrate surrounding a lower portion of the metal insulator-metal capacitor.

8. The nonvolatile memory device of claim 7 further comprising:
a second isolation region in the active layer of the substrate, wherein the second isolation region is adjacent to an upper portion of the first isolation region.

9. The nonvolatile memory device of claim 8 , wherein the first isolation region and the second isolation region are between the lower portion of the metal-insulator-metal capacitor and the first active region below the floating gate.

10. The nonvolatile memory device of claim 1 , wherein the first electrode of the metal-insulator-metal capacitor is conformal to a side surface and a bottom surface of the metal-insulator metal capacitor.

11. An array of nonvolatile memory devices comprising:
a first active region and a second active region in an active layer of a substrate;
a first isolation region and a second isolation region adjacent to the first isolation region between the first active region and the second active region;
a first array of floating gates over the first active region and a second array of floating gates over the second active region;
a metal-insulator-metal capacitor laterally adjacent to the floating gates, wherein a lower portion of the metal-insulator-metal capacitor is in the first isolation region in the active layer and a first dielectric layer in the substrate; and
a contact pillar connecting a first electrode of the metal-insulator-metal capacitor to each floating gate.

12. The nonvolatile memory device of claim 11 , wherein the metal-insulator-metal capacitor extends across at least part of a length of the first active region and the second active region.

13. The nonvolatile memory device of claim 12 , wherein the substrate comprises the first dielectric layer and the active layer over the first dielectric layer.

14. The nonvolatile memory device of claim 13 , wherein the lower portion of the metal-insulator-metal capacitor extends vertically in the active layer and an upper portion of the first dielectric layer in the substrate.

15. The nonvolatile memory device of claim 14 , wherein an upper portion of the metal-insulator-metal capacitor extends vertically in an inter layer dielectric (ILD) layer above the substrate.

16. The nonvolatile memory device of claim 15 , wherein the upper portion of the metal-insulator-metal capacitor further comprises:
an extension portion extending laterally in an inter metal dielectric (IMD) layer above the inter layer dielectric layer and at least partially overlaps laterally with the floating gates.

Assignees

• Globalfoundries Sg Pte Ltd
• Globalfoundries Singapore Ptd Ltd

Inventors

• Mun Bong Woong
• Koo Jeoung Mo

Classifications

• H01L29/66825

  Electricity · mapped topic

• H01L27/11521 Primary

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic

• H01L28/60

  Electricity · mapped topic

• H01L29/7885

  Electricity · mapped topic