Architecture and processes to enable high capacity memory packages through memory die stacking

Patent metadata

Field	Value
Publication number	US-11456281-B2
Application number	US-201816147742-A
Country	US
Kind code	B2
Filing date	Sep 29, 2018
Priority date	Sep 29, 2018
Publication date	Sep 27, 2022
Grant date	Sep 27, 2022

Abstract

Embodiments include electronic packages and methods of forming such packages. An electronic package includes a memory module comprising a first memory die. The first memory die includes first interconnects with a first pad pitch and second interconnects with a second pad pitch, where the second pad pitch is less than the first pad pitch. The memory module also includes a redistribution layer below the first memory die, and a second memory die below the redistribution layer, where the second memory die has first interconnects with a first pad pitch and second interconnects with a second pad pitch. The memory module further includes a mold encapsulating the second memory die, where through mold interconnects (TMIs) provide an electrical connection from the redistribution layer to mold layer. The TMIs may be through mold vias. The TMIs may be made through a passive interposer that is encapsulated in the mold.

First claim

What is claimed is:

1. A memory module, comprising:
a first memory die having first interconnects with a first pad pitch and second interconnects with a second pad pitch, wherein the second pad pitch is less than the first pad pitch;
a redistribution layer below the first memory die;
a second memory die below the redistribution layer, wherein the second memory die has first interconnects with a first pad pitch and second interconnects with a second pad pitch; and
a mold layer encapsulating the second memory die, wherein through mold interconnects provide an electrical connection from the redistribution layer to a bottom surface of the mold layer.

2. The memory module of claim 1 , wherein the through mold interconnects are through mold vias.

3. The memory module of claim 2 , wherein the through mold interconnects are made through a passive interposer that is encapsulated in the mold layer.

4. The memory module of claim 3 , wherein the passive interposer comprises silicon.

5. The memory module of claim 1 , wherein the second interconnects of the first memory die are along an edge portion of the memory die.

6. The memory module of claim 1 , further comprising an adhesive layer disposed between the second memory die and the redistribution layer, wherein the adhesive layer directly couples a top surface of the second memory die to a bottom surface of the redistribution layer.

7. The memory module of claim 5 , wherein the second interconnects of the second memory die are along an edge portion of the memory die.

8. The memory module of claim 7 , wherein the second interconnects of the first memory die are above the second interconnects of the second memory die, and wherein the first and second memory dies are high bandwidth low latency (HBLL) memory dies.

9. The memory module of claim 1 , further comprising a second mold layer encapsulating the first memory die.

10. An electronic package, comprising:
a package substrate;
a SoC die on the package substrate;
a memory module on the package substrate, wherein the memory module comprises:
a plurality of memory dies, wherein each die has first interconnects with a first pad pitch and second interconnects with a second pad pitch that is smaller than the first pad pitch; and
a bridge substrate, wherein the second interconnects of the memory dies are electrically coupled to the SoC die by the bridge substrate.

11. The electronic package of claim 10 , wherein the bridge substrate is embedded in the package substrate.

12. The electronic package of claim 10 , wherein the bridge substrate is in the package substrate, and wherein the SoC die is above the bridge substrate.

13. The electronic package of claim 10 , wherein the plurality of memory dies includes a first memory die and a second memory die, and wherein the first and second memory dies are HBLL memory dies.

14. The electronic package of claim 13 , wherein the first memory die is laterally surrounded by a first mold layer, a redistribution layer is over the first mold layer, and the second memory die is over the redistribution layer.

15. The electronic package of claim 14 , further comprising a through mold interconnect providing an electrical connection from the redistribution layer to a surface of the first mold layer opposite from the redistribution layer.

16. The electronic package of claim 15 , wherein the through mold interconnect is a through mold via.

Assignees

• Intel Corp

Inventors

• Li Yí
• Qian Zhiguo
• Ramanathan Prasad
• Jayaraman Saikumar
• Aygun Kemal
• Amador Hector
• Collins Andrew
• Xie Jianyong
• Tomishima Shigeki

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/721

  of bump connectors · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title