Method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-11456264-B2
Application number	US-202117148923-A
Country	US
Kind code	B2
Filing date	Jan 14, 2021
Priority date	Feb 27, 2020
Publication date	Sep 27, 2022
Grant date	Sep 27, 2022

Abstract

In a method of manufacturing a semiconductor device according to one embodiment, after a semiconductor wafer including a non-volatile memory, a bonding pad and an insulating film comprised of an organic material is provided, a probe needle is contacted to a surface of the bonding pad located in a second region, and a data is written to the non-volatile memory. Here, the insulating film is formed by performing a first heat treatment to the organic material. Also, after a second heat treatment is performed to the semiconductor wafer, and the non-volatile memory to which the data is written is checked, a barrier layer and a first solder material are formed on the surface of the bonding pad located in a first region by using an electroplating method. Further, a bump electrode is formed in the first region by performing a third heat treatment to the first solder material.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
step (a) providing a semiconductor wafer including:
a semiconductor substrate;
a non-volatile memory formed in the semiconductor substrate;
a bonding pad formed on the semiconductor substrate, and electrically connected with the non-volatile memory, and comprised of aluminum; and
an insulating film formed on the semiconductor substrate, and comprised of an organic material,

wherein a surface of the bonding pad has:
a first region exposed in a first opening portion of the insulating film; and
a second region exposed in a second opening portion of the insulating film, which is different from the first opening portion, and

wherein the insulating film is formed by performing a first heat treatment to the organic material;
step (b) after the step (a), writing a data to the non-volatile memory by contacting a probe needle to the surface of the bonding pad located in the second region;
step (c) after the step (b), performing a second heat treatment to the semiconductor wafer, and checking the non-volatile memory to which the data is written in the step (b),
wherein a temperature of the second heat treatment is lower than a temperature of the first heat treatment, and
wherein a time of the second heat treatment is longer than a time of the first heat treatment;
step (d) after the step (c), forming a barrier layer comprised of nickel on the surface of the bonding pad located in the first region by using an electroplating method;
step (e) after the step (d), forming a first solder material comprised of tin on the barrier layer by using the electroplating method; and
step (f) after the step (e), forming a bump electrode on the surface of the bonding pad located in the first region via the barrier layer by performing a third heat treatment to the first solder material,
wherein a temperature of the third heat treatment is lower than the temperature of the first heat treatment, and
wherein a time of the third heat treatment is shorter than the time of the second heat treatment.

2. The method according to claim 1 ,
wherein the non-volatile memory is comprised of:
a floating gate electrode formed on the semiconductor substrate via a tunnel oxide film comprised of silicon oxide;
a control gate electrode formed on the floating gate electrode via one of an interlayer insulating film made of silicon oxide and an interlayer insulating film made of silicon oxide and silicon nitride;
a source region formed in a first portion of the semiconductor substrate, which is located on one side of the floating gate electrode; and
a drain region formed in a second portion of the semiconductor substrate, which is located on another side of the floating gate electrode, and

wherein a thickness of the tunnel oxide film is less than or equal to 10 nm.

3. The method according to claim 2 further comprising:
step (g) after the step (c) and before the step (d), forming a seed layer on the semiconductor substrate by using PVD (Physical Vapor Deposition) method,
wherein each of the step (d) and the step (e) is performed in a state that the surface of the bonding pad located in the second region is covered with a mask, and in a state that the surface of the bonding pad located in the first region is exposed from the mask, and
wherein a portion of the seed layer, which is exposed from each of the first solder material and the barrier layer is removed after the step (e) and before the step (f).

4. The method according to claim 3 further comprising:
step (h) after the step (f), obtaining a semiconductor chip having the bump electrode, the barrier layer, the bonding pad and the non-volatile memory by cutting the semiconductor wafer; and
step (i) after the step (h), mounting the semiconductor chip obtained by the step (h) on an interposer via the bump electrode,
wherein in the step (i), a vertical load is applied to the semiconductor chip.

5. The method according to claim 4 further comprising:
step (j) after the step (i), sealing a gap between the semiconductor chip and the interposer with a resin having a plurality of fillers.

6. The method according to claim 5 ,
wherein the interposer has:
an upper surface on which the semiconductor chip is mounted;
a lower surface opposite the upper surface; and
a bump land formed on the lower surface,
wherein the method according to claim 5 further comprising:
step (k) after the step (j), forming a second solder material comprised of tin on the bump land; and
step (l) after the step (k), forming an external connection terminal on the bump land by performing a fourth heat treatment to the second solder material,
wherein a temperature of the fourth heat treatment is 100° C. to 270° C., and
wherein a time of the fourth heat treatment is several tens of seconds to 5 minutes.

7. A method of manufacturing a semiconductor device, the method comprising:
step (a) providing a semiconductor wafer including:
a semiconductor substrate;
a non-volatile memory formed in the semiconductor substrate;
a bonding pad formed on the semiconductor substrate, and electrically connected with the non-volatile memory, and comprised of aluminum; and
an insulating film formed on the semiconductor substrate, and comprised of an organic material,

wherein a surface of the bonding pad has:
a first region exposed in a first opening portion of the insulating film; and
a second region exposed in a second opening portion of the insulating film, which is different from the first opening portion,

wherein after arranging the organic material on the semiconductor substrate, the insulating film is formed by performing a first heat treatment to the organic material,
wherein a temperature of the first heat treatment is 300° C. to 400° C., and
wherein a time of the first heat treatment is 30 minutes to 2 hours;
step (b) after the step (a), writing a data to the non-volatile memory by contacting a probe needle to the surface of the bonding pad located in the second region;
step (c) after the step (b), performing a second heat treatment to the semiconductor wafer, and checking the non-volatile memory to which the data is written in the step (b),
wherein a temperature of the second heat treatment is 200° C. to 280° C., and
wherein a time of the second heat treatment is 6 hours to 50 hours;
step (d) after the step (c), forming a conductive film comprised of nickel on the surface of the bonding pad located in the first region by using an electroplating method;
step (e) after the step (d), forming a first solder material comprised of tin on the conductive film by using the electroplating method;
step (f) after the step (e), forming a bump electrode on the surface of the bonding pad located in the first region via the conductive film by performing a third heat treatment to the first solder material,
wherein a temperature of the third heat treatment is 100° C. to 270° C., and
wherein a time of the third heat treatment is several tens of seconds to 5 minutes; and
step (g) after the step (f), obtaining a semiconductor chip having the bump electrode, the conductive film, the bonding pad and the non-volatile memory by cutting the semiconductor wafer.

8. The method according to claim 7 ,
wherein the non-volatile memory is comprised of:
a floating gate electrode formed on the semiconductor substrate via a tunnel oxide film made of silicon oxide;
a control gate electrode formed on the floating gate electrode via one of an interlayer insulating film made of silicon oxide and an interlayer insulating film made of silicon oxide and silicon nitride;
a source region formed in a first portion of the semiconductor substrate, which is

Assignees

• Renesas Electronics Corp

Inventors

• Sato Yoshiaki
• Wansawa Mitsunobu
• Matsumoto Akira
• Deguchi Yoshinori
• Saito Kentaro

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/07232

  Compression bonding, e.g. thermocompression bonding · CPC title

• H10W72/01265

  Thermally treating (reflowing H10W72/01257) · CPC title

• H10W72/01235

  by plating, e.g. electroless plating or electroplating · CPC title