Method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9711377-B2
Application number	US-201514886088-A
Country	US
Kind code	B2
Filing date	Oct 18, 2015
Priority date	Nov 7, 2014
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Provided is a semiconductor device with improved reliability that achieves the reduction in size. A semiconductor wafer is provided that has a first insulating member with an opening that exposes from which an upper surface of an electrode pad. Subsequently, after forming a second insulating member over a main surface of the semiconductor wafer, another opening is formed to expose the upper surface of the electrode pad. Then, a probe needle is brought into contact with the electrode pad, to write data in a memory circuit at the main surface of the semiconductor wafer. After covering the upper surface of the electrode pad with a conductive cover film, a relocation wiring is formed. In the Y direction, the width of the relocation wiring positioned directly above the electrode pad is equal to or smaller than the width of the opening formed in the first insulating member.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
(a) providing a semiconductor wafer including a main surface, a first electrode pad formed over the main surface, a second electrode pad formed over the main surface and also arranged next to the first electrode pad in plan view, and a first insulating member including a first opening that exposes an upper surface of the first electrode pad and a second opening that exposes an upper surface of the second electrode pad;
(b) after (a), forming a second insulating member over the first insulating member of the semiconductor wafer, and forming a third opening that exposes the upper surface of the first electrode pad and a fourth opening that exposes the upper surface of the second electrode pad, in the second insulating member;
(c) after (b), bringing probe needles into contact with the first and second electrode pads, respectively, thereby writing data in a memory circuit of the semiconductor wafer;
(d) after (c), within the third opening and the fourth opening, covering the upper surface of the first electrode pad and the upper surface of the second electrode pad with a first cover film and a second cover film, respectively;
(e) after (d), forming a first wiring and a second wiring over a surface of the first cover film and a surface of the second cover film, respectively; and
(f) after (e), covering the surface of the first cover film, the surface of the second cover film, the first wiring and the second wiring with a third insulating member, and forming a fifth opening that exposes a first part of the first wiring and a sixth opening that exposes a first part of the second wiring, in the third insulating member,
wherein, in plan view, the first electrode pad and the second electrode pad are arranged along a first direction,
wherein each of the first cover film and the second cover film is comprised of a conductive material,
wherein the first part of the first wiring is located outside of the third opening in plan view and is formed over the second insulating member,
wherein the first wiring has a second part located within the third opening in plan view,
wherein the first part of the second wiring is located outside of the fourth opening in plan view and is formed over the second insulating member,
wherein the second wiring has a second part located within the fourth opening in plan view,
wherein, in plan view, a width of the second part of the first wiring in the first direction is equal to or smaller than a width of the third opening formed in the second insulating member, wherein, in plan view, a width of the second part of the second wiring in the first direction is equal to or smaller than a width of the fourth opening formed in the second insulating member, and
wherein in (b) a heat treatment is performed.

2. The method of manufacturing a semiconductor device according to claim 1 ,
wherein an opening end of the first opening formed in the first insulating member is positioned within an opening end of the third opening formed in the second insulating member, and
wherein an opening end of the second opening formed in the first insulating member is positioned within an opening end of the fourth opening formed in the second insulating member.

3. The method of manufacturing a semiconductor device according to claim 1 ,
wherein the first insulating member has a first elastic modulus, and the second insulating member has a second elastic modulus lower than the first elastic modulus.

4. The method of manufacturing a semiconductor device according to claim 1 ,
wherein the first insulating member is an inorganic insulating film, and the second insulating member is an organic insulating film.

5. The method of manufacturing a semiconductor device according to claim 1 ,
wherein the first cover film and/or the second cover film is a laminated film including a nickel film.

6. The method of manufacturing a semiconductor device according to claim 1 ,
wherein (e) comprises:
(e1) forming a first seed layer at the surface of the first cover film and the surface of the second insulating member, and a second seed layer at the surface of the second cover film;
(e2) forming the first wiring and the second wiring on the first seed layer and the second seed layer, respectively; and
(e3) removing a part of the first seed layer not overlapping with the first wiring, and a part of the second seed layer not overlapping with the second wiring.

7. The method of manufacturing a semiconductor device according to claim 1 , further comprising:
(h) after (f), electrically coupling respective bump electrodes to the first part of the first wiring exposed from the fifth opening and the first part of the second wiring exposed from the sixth opening.

8. The method of manufacturing a semiconductor device according to claim 1 , further comprising, after (f):
(i) cutting the semiconductor wafer along a scribe region between partitioned device regions, thereby obtaining a plurality of semiconductor chips;
(j) fixing one of the plurality of semiconductor chips in a chip mounting region of a wiring board; and
(k) for said one of the plurality of semiconductor chips, electrically coupling the first part of the first wiring exposed from the fifth opening, the first part of the second wiring exposed from the sixth opening, and a plurality of electrodes formed around the chip mounting region of the wiring board to one another using conductive material.

9. The method of manufacturing a semiconductor device according to claim 1 ,
wherein, in plan view, a width of the first part of the first wiring is larger than the width of the second part of the first wiring, and
wherein, in plan view, a width of the first part of the second wiring is larger than the width of the second part of the second wiring.

Assignees

• Renesas Electronics Corp

Inventors

• Akiba Toshihiko
• Shigihara Hiromi
• Yajima Kei

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/075 Primary

  of bond wires · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/0198

  batch processes · CPC title