Methods for fabrication of bonded wafers and surface acoustic wave devices using same

Patent metadata

Field	Value
Publication number	US-11451206-B2
Application number	US-201916507678-A
Country	US
Kind code	B2
Filing date	Jul 10, 2019
Priority date	Jul 28, 2015
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

A method of fabricating a bonded wafer with low carrier lifetime in silicon comprises providing a silicon substrate having opposing top and bottom surfaces, modifying a top portion of the silicon substrate to reduce carrier lifetime in the top portion relative to the carrier lifetime in portions of the silicon substrate other than the top portion, bonding a piezoelectric layer having opposing top and bottom surfaces separated by a distance T over the top surface of the silicon substrate, and providing a pair of electrodes having fingers that are inter-digitally dispersed on a top surface of the piezoelectric layer, the electrodes comprising a portion of a Surface Acoustic Wave (SAW) device. The modifying and bonding steps may be performed in any order. The modified top portion of the silicon substrate prevents the creation of a parasitic conductance within that portion during operation of the SAW device.

First claim

What is claimed is:

1. A method of fabricating a bonded wafer with low carrier lifetime in silicon, the method comprising:
providing a silicon substrate having opposing top and bottom surfaces;
modifying a top portion of the silicon substrate to impair an ability of the top portion to behave like a semiconductor by forming locations in the top portion which trap free carriers;
providing a piezoelectric layer over the top surface of the silicon substrate, the piezoelectric layer having opposing top and bottom surfaces separated by a distance T; and
providing a pair of electrodes having fingers that are inter-digitally dispersed on the top surface of the piezoelectric layer in a pattern having a center-to-center distance D between adjacent fingers of the same electrode, the electrodes comprising a portion of a Surface Acoustic Wave (SAW) device, the modified top portion of the silicon substrate preventing creation of a parasitic conductance within the top portion of the silicon substrate during operation of the SAW device,
wherein modifying the top portion of the silicon substrate comprises providing metal ions in the top portion of the silicon substrate that cause deep trap impurities to be included in the top portion of the silicon substrate.

2. The method of claim 1 wherein a thickness of the modified top portion is at least 10 nanometers.

3. The method of claim 1 wherein a thickness of the modified top portion is at least 50 nanometers.

4. The method of claim 1 wherein a thickness of the modified top portion is at least 200 nanometers.

5. The method of claim 1 wherein providing the piezoelectric layer comprises providing a layer comprising at least one of quartz, lithium niobate (LiNbO 3 ), or lithium tantalate (LiTaO 3 ).

6. The method of claim 1 wherein T<(2*D).

7. The method of claim 1 wherein T>(0.10*D).

8. The method of claim 1 wherein:
T <(1.76−2.52 e− 4*( V SUB +4210− V PIEZO ))* D;

V SUB is a velocity of a slowest acoustic wave in a propagation direction in the silicon substrate; and
V PIEZO is a SAW velocity in the piezoelectric layer.

9. The method of claim 1 further comprising providing an insulation layer between the silicon substrate and the piezoelectric layer, wherein providing the metal ions in the top portion of the silicon substrate comprises one of:
implanting the metal ions through the insulation layer and into the top portion of the silicon substrate;
implanting the metal ions through the piezoelectric layer and into the top portion of the silicon substrate; or
implanting the metal ions through the piezoelectric layer and the insulation layer and into the top portion of the silicon substrate.

10. A method of fabricating a bonded wafer with low carrier lifetime in silicon, the method comprising:
providing a silicon substrate having opposing top and bottom surfaces;
providing an insulation layer over the top surface of the silicon substrate;
modifying a top portion of the silicon substrate to impair an ability of the top portion to behave like a semiconductor by forming locations in the top portion which trap free carriers;
providing a piezoelectric layer over a top surface of the insulation layer, the piezoelectric layer having opposing top and bottom surfaces separated by a distance T; and
providing a pair of electrodes having fingers that are inter-digitally dispersed on the top surface of the piezoelectric layer in a pattern having a center-to-center distance D between adjacent fingers of the same electrode, the electrodes comprising a portion of a Surface Acoustic Wave (SAW) device, the modified top portion of the silicon substrate preventing creation of a parasitic conductance within the top portion of the silicon substrate during operation of the SAW device,
wherein modifying the top portion of the silicon substrate comprises implanting ions through at least the insulation layer and into the top portion of the silicon substrate.

11. The method of claim 10 wherein:
the silicon substrate is monocrystalline; and
implanting the ions into the top portion of the silicon substrate causes the top portion to comprise a non-monocrystalline structure having the locations which trap free carriers.

12. The method of claim 11 wherein the top portion is modified to have a defect density in a range from 1e17/cm 3 to 1e22/cm 3 .

13. The method of claim 11 wherein modifying the top portion of the silicon substrate comprises implanting the ions through the piezoelectric layer and the insulation layer and into the top portion of the silicon substrate.

14. The method of claim 13 wherein the ions are implanted across a thickness of the top portion of the silicon substrate.

15. The method of claim 13 wherein implanting the ions into the top portion of the silicon substrate causes a defect density in a range from 1e17/cm 3 to 1e22/cm 3 .

16. The method of claim 10 wherein implanting the ions into the top portion of the silicon substrate comprises implanting metal ions into the top portion of the silicon substrate that cause deep trap impurities to be included in the top portion of the silicon substrate.

17. The method of claim 16 wherein the top portion is modified to have an impurity density in a range from 1e15/cm 3 to 1e18/cm 3 .

18. The method of claim 10 wherein the modified top portion has a carrier lifetime of less than 100 nanoseconds.

19. A method of fabricating a bonded wafer with low carrier lifetime in silicon, the method comprising:
providing a silicon substrate having opposing top and bottom surfaces;
modifying a top portion of the silicon substrate to reduce carrier lifetime across a thickness of the top portion relative to a carrier lifetime in portions of the silicon substrate other than the top portion;
providing a piezoelectric layer over the top surface of the silicon substrate, the piezoelectric layer having opposing top and bottom surfaces separated by a distance T; and
providing a pair of electrodes having fingers that are inter-digitally dispersed on the top surface of the piezoelectric layer in a pattern having a center-to-center distance D between adjacent fingers of the same electrode, the electrodes comprising a portion of a Surface Acoustic Wave (SAW) device, the modified top portion of the silicon substrate preventing creation of a parasitic conductance within the top portion of the silicon substrate during operation of the SAW device,
wherein modifying the top portion of the silicon substrate comprises providing metal ions in the top portion of the silicon substrate that cause deep trap impurities to be included within the top portion of the silicon substrate.

20. The method of claim 19 further comprising providing an insulation layer between the silicon substrate and the piezoelectric layer, wherein the modifying and providing the insulation layer steps are performed in any order.

21. The method of claim 20 wherein providing the insulation layer comprises providing a layer of silicon oxide.

22. The method of claim 21 further comprising doping the layer of silicon oxide with Fluorine or Boron compounds to reduce thermal sensitivity of the SAW device.

23. The method of claim 20 wherein a thickness of the insulation layer is greater than (0.02*D).

24. The method of claim 23 wherein providing the insulation layer comprises providing a layer of silicon oxide.

25. The method of claim 20 wherein:
T <(1.76−2.52 e− 4*( V

Assignees

• Qorvo Us Inc

Inventors

• Inoue Shogo
• Solal Marc
• Aigner Robert

Classifications

• H03H9/02834

  of temperature influence (cut angles H03H9/02543) · CPC title

• H03H9/17

  having a single resonator (crystal tuning forks H03H9/21) · CPC title

• H03H9/54

  comprising resonators of piezoelectric or electrostrictive material (comprising resonators using surface acoustic waves H03H9/64) · CPC title

• H03H9/02952

  of parasitic capacitance · CPC title

• H03H9/25

  Constructional features of resonators using surface acoustic waves {(devices for manipulating acoustic surface waves in general G10K11/36)} · CPC title