One transistor and one ferroelectric capacitor memory cells in diagonal arrangements

Patent metadata

Field	Value
Publication number	US-11450675-B2
Application number	US-201816132281-A
Country	US
Kind code	B2
Filing date	Sep 14, 2018
Priority date	Sep 14, 2018
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

Described herein are one access transistor and one ferroelectric capacitor (1T-1FE-CAP) memory cells in diagonal arrangements, as well as corresponding methods and devices. When access transistors of memory cells are implemented as FinFETs, then, in a first diagonal arrangement, memory cells are arranged so that the BLs for the cells are diagonal with respect to the fins of the access transistors of the cells, while the WLs for the cells are perpendicular to the fins. In a second diagonal arrangement, memory cells are arranged so that the fins of the access transistors of the cells are diagonal with respect to the WLs for the cells, while the BLs for the cells are perpendicular to the WLs. Such diagonal arrangements may advantageously allow achieving high layout densities of 1T-1FE-CAP memory cells and may benefit from the re-use of front-end transistor process technology with relatively minor adaptations.

First claim

The invention claimed is:

1. An integrated circuit (IC) device, comprising:
a base; and
a plurality of memory cells, each memory cell comprising:
a transistor, and
a capacitor comprising a first capacitor electrode, a second capacitor electrode, and a ferroelectric material between the first and second capacitor electrodes, where the transistor includes a first source/drain (S/D) terminal coupled to a bitline (BL) and further includes a second S/D terminal coupled to the capacitor,

wherein:
a second S/D terminal of a first memory cell of the plurality of memory cells is closer to a second S/D terminal of a second memory cell of the plurality of memory cells than the first S/D terminal of the first memory cell,
the second SID terminal of the second memory cell is closer to the second S/D terminal of the first memory cell than the first S/D terminal of the second memory cell,
a transistor of the first memory cell and a transistor of the second memory cell include a continuous fin of a semiconductor material, the fin extending away from the base,
a projection of the BL onto the base is at an angle between 5 and 45 degrees with respect to an edge of the base, and
a projection of the fin onto the base is at an angle of substantially 90 degrees with respect to the edge of the base.

2. The IC device according to claim 1 , wherein the projection of the BL onto the base is at an angle between 10 and 30 degrees with respect to the projection of the fin onto the base.

3. The IC device according to claim 1 , further comprising at least a first interconnect layer and a second interconnect layer above the base, wherein the first interconnect layer is between the base and the second interconnect layer, and wherein the BL is in the first interconnect layer.

4. The IC device according to claim 3 , wherein the second capacitor electrode is in the second interconnect layer or in a third interconnect layer that is farther away from the base than the second interconnect layer.

5. The IC device according to claim 3 , further comprising one or more conductive vias extending through at least the first interconnect layer to couple the second capacitor electrode to the second S/D terminal of the transistor of the first memory cell.

6. The IC device according to claim 1 , wherein the BL has a first face and an opposing second face, the first face is closer to the base than the second face, and the memory device further includes an etch stop material over at least a portion of the second face of the BL.

7. The IC device according to claim 6 , wherein the memory device further includes the etch stop material over at least a portion of at least one sidewall of the BL, and the sidewall extends between the second face and the first face.

8. The IC device according to claim 6 , wherein the memory device further includes a BL contact coupling the BL and the first S/D terminal of the transistor of the first memory cell, and wherein the etch stop material at least partially wraps around the BL and the BL contact.

9. The IC device according to claim 1 , wherein the transistor of the first memory cell further includes a gate terminal coupled to a wordline (WL), and wherein the projection of the fin onto the base is perpendicular to a projection of the WL onto the base.

10. The IC device according to claim 1 , wherein the first S/D terminal is a source terminal.

11. The IC device according to claim 1 , wherein the ferroelectric material comprises one or more of:
a ferroelectric material comprising hafnium, zirconium, and oxygen;
a ferroelectric material comprising hafnium, silicon, and oxygen;
a ferroelectric material comprising hafnium, germanium, and oxygen;
a ferroelectric material comprising hafnium, aluminum, and oxygen; or
a ferroelectric material comprising hafnium, yttrium, and oxygen.

12. The IC device according to claim 1 , wherein the ferroelectric material has a thickness between 1 nanometer and 10 nanometers.

13. The IC device according to claim 1 , wherein the first capacitor electrode is coupled to a plateline.

14. The IC device according to claim 1 , further comprising a package substrate and an IC die coupled to the package substrate, wherein the IC die includes the base and the plurality of memory cells.

15. The IC device according to claim 1 , wherein the IC device is a computing device.

16. The IC device according to claim 15 , wherein the computing device is a wearable device or a handheld computing device.

17. The IC device according to claim 1 , wherein the IC device is a wearable device or a handheld computing device.

18. A method of operating a memory device comprising a base, a first memory cell, and a second memory cell, each of the first memory cell and the second memory cell comprising a transistor and a capacitor, the transistor including a first source/drain (S/D) terminal and a second S/D terminal, the method comprising:
driving a wordline (WL), coupled to a gate terminal of the transistor of the first memory cell, to cause the transistor of the first memory cell to turn on; and
programming the capacitor of the first memory cell by, when the transistor of the first memory cell is turned on, driving a bitline (BL) coupled to the first S/D terminal of the transistor of the first memory cell to charge or discharge an intermediate node coupled to the second S/D terminal of the transistor of the first memory cell,
wherein:
the second S/D terminal of the first memory cell is closer to the second S/D terminal of the second memory cell than the first S/D terminal of the first memory cell,
the second S/D terminal of the second memory cell is closer to the second S/D terminal of the first memory cell than the first S/D terminal of the second memory cell,
the transistor of the first memory cell and the transistor of the second memory cell includes a continuous fin of a semiconductor material, the fin extending away from the base,
a projection of the WL onto the base is substantially perpendicular to a projection of the fin onto the base, and
a projection of the BL onto the base is at an angle between 5 and 45 degrees with respect to the projection of the fin onto the base.

19. The method according to claim 18 , wherein a first capacitor electrode of the capacitor of the first memory cell is coupled to a plateline (PL), a second capacitor electrode of the capacitor of the first memory cell is coupled to the intermediate node, and a ferroelectric material is between the first capacitor electrode and the second capacitor electrode.

20. The method according to claim 19 , wherein programming the capacitor of the first memory cell includes applying a first voltage to the PL to generate an electric field across the ferroelectric material, and wherein driving the WL and driving the BL are performed after applying the first voltage to the PL.

21. The method according to claim 20 , wherein application of the first voltage to the PL causes a first logic state to be programmed on the capacitor of the first memory cell, the method further comprising applying a second voltage to the PL after applying the first voltage to the PL, wherein application of the second voltage to the PL together with driving the WL and the BL causes a second logic state to be programmed on the capacitor of the first memory cell.

22. The method according to claim 19 , wherein programming the capacitor of the first memory cell comprises:
applying a first voltage to the PL to ensure that a polarization of the

Assignees

• Intel Corp

Inventors

• Morris Daniel H
• Avci Uygar E
• Young Ian A

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/655

  Fan-out layouts · CPC title