Multi-ported nonvolatile memory device with bank allocation and related systems and methods

Patent metadata

Field	Value
Publication number	US-11449441-B2
Application number	US-202117327460-A
Country	US
Kind code	B2
Filing date	May 21, 2021
Priority date	Aug 5, 2019
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

A memory device that includes a first port and a second port. The first port includes a first clock input, at least one first command address input, and at least one data input or output configured to transfer data in relation to the memory device. The second port includes a second clock input and at least one command, address, and data input/output (I/O) configured to receive command and address information from, and to transfer data in relation to the memory device. The memory device also includes a plurality of memory banks, in which two different memory banks may be accessed respectively by the first and the second ports concurrently. Other embodiments of the memory device and related methods and systems are also disclosed.

First claim

What is claimed is:

1. A memory device, comprising:
a first port of a first type including:
a first clock input;
at least one first command address input configured to receive command and address information; and
at least one data input or output configured to transfer data in relation to the memory device;

a second port of a second type including:
a second clock input;
at least one command, address, and data input/output (I/O) configured to receive command and address information from, and to transfer data in relation to the memory device;

a memory including a plurality of banks, wherein each bank is configurable for access by the first port or the second port based on an access value, and wherein a first bank and a second bank of the plurality of banks are accessible respectively by the first and second ports at least in part concurrently based on their respective access values; and
a bank access register configured to store the access value of each bank of the memory.

2. The memory device of claim 1 , wherein the first port includes at least one parallel port and the at least one data input or output includes parallel data inputs/outputs (I/Os) configured to send data to write to the plurality of banks during write operations and receive read data from the plurality of banks during read operations of the memory device.

3. The memory device of claim 1 , wherein the first port includes at least one parallel port and the at least one data input or output includes unidirectional data outputs configured to output read data from the memory device in parallel.

4. The memory device of claim 1 , wherein the first port is compatible with at least a portion of a low power DDR interface (LPDDR) standard.

5. The memory device of claim 1 , wherein when a bank of the plurality of banks is configured for access by the first port, the bank is not accessible by the second port.

6. The memory device of claim 1 , wherein the second port includes at least one serial port and the at least one command, address, and data I/O includes serial data inputs/outputs (I/Os) configured to send data to write to the plurality of banks during write operations and receive read data from the plurality of banks during read operations of the memory device.

7. The memory device of claim 3 , wherein the second port includes at least one serial port and the at least one command, address, and data I/O includes serial data inputs/outputs (I/Os) configured to send data to write to the plurality of banks during write operations and receive read data from the plurality of banks during read operations of the memory device.

8. The memory device of claim 1 , wherein the second port is compatible with a Serial Peripheral Interconnect (SPI) standard.

9. The memory device of claim 1 , wherein the memory includes non-volatile memory cells.

10. A system, comprising:
a processing device; and
a memory device, coupled to the processing device, including:
a first port coupled to a first interface configured to receive command, address, and write data from, and to transmit read data to the processing device;
a read/write parallel port coupled to a parallel double data rate (DDR) interface configured to receive command, address, and write data from, and to transmit read data to the processing device;
a non-volatile memory (NVM) array including a plurality of banks, wherein each bank is configured for access based on a corresponding access value, and wherein two different banks of the plurality of banks are configured to enable access respectively by the first port and the read/write parallel port concurrently; and
a bank access register configured to store the corresponding access value for each bank of the plurality of banks.

11. The system of claim 10 , wherein each bank of the plurality of banks is configured to enable access by only one of the first interface or the parallel DDR interface in a same time period.

12. The system of claim 10 , wherein the first port includes a serial read/write port, the first interface is a Serial Peripheral Interconnect (SPI) interface compatible with a SPI standard.

13. The system of claim 10 , wherein the first port includes a read-only parallel port and the first interface is a unidirectional parallel DDR interface.

14. The system of claim 10 , wherein the parallel DDR interface is compatible with at least a portion of a low power DDR interface (LPDDR) standard.

15. The system of claim 10 , wherein the processing device comprises one or more cores configured to control different parts of an automobile.

16. The system of claim 10 , wherein the memory device further comprises a logic element configured to set access values for at least one bank in response to command and address information received from the processing device via the first interface and the parallel DDR interface.

17. A method of operating a non-volatile memory (NVM) device, comprising:
receiving a first access command and address information to a first memory bank through a first port of the NVM device;
setting, by a logic element in the NVM device based at least partly on the first access command and address information, a first access value stored in a bank access register for the first memory bank;
enabling access to the first memory bank via the first port based at least partly on the first access value;
receiving a second access command and address information to a second memory bank through a second port of the NVM device;
setting, by the logic element based at least partly on the second access command and address information, a second access value stored in the bank access register for the second memory bank;
and
enabling concurrent access to the second memory bank via the second port based at least partly on the second access value when the first memory bank is being accessed via the first port, wherein the first memory bank is different from the second memory bank.

18. The method of claim 17 , wherein the first port is a parallel port and the second port is a serial port.

19. The method of claim 17 , wherein the first port is a unidirectional parallel port configured for data output from the NVM device and the second port is a parallel port.

20. The method of claim 17 , further comprising:
disabling access to the first memory bank via the second port when the first memory bank is being accessed via the first port; and
disabling access to the second memory bank via the first port when the second memory bank is being accessed via the second port.

Assignees

• Cypress Semiconductor Corp

Inventors

• Betser Yoram
• Zitlaw Cliff
• Rosner Stephan
• Danon Kobi
• Rochman Amir

Classifications

• G06F13/4234

  being a memory bus · CPC title

• G06F2213/0004

  Parallel ports, e.g. centronics · CPC title

• G06F13/4291

  using a clocked protocol · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F2213/0002

  Serial port, e.g. RS232C · CPC title