Multi-ported nonvolatile memory device with bank allocation and related systems and methods

Patent metadata

Field	Value
Publication number	US-11030128-B2
Application number	US-201916719493-A
Country	US
Kind code	B2
Filing date	Dec 18, 2019
Priority date	Aug 5, 2019
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.

First claim

What is claimed is:

1. A nonvolatile memory device, comprising:
a serial port including
at least one serial clock input, and
at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input;

at least one parallel port including
a plurality of command address inputs configured to receive command and address data in groups of parallel bits,
a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal; and

plurality of banks, each bank including a plurality of nonvolatile memory cells and configurable for access by the at least one serial port or the at least one parallel port, wherein when a bank is configured for access by the at least one serial port, the bank is not accessible by the at least one parallel port and;
a bank access register configured to store access values for each bank, wherein each bank is accessible by the serial port or the parallel port based on the access value for the bank stored in the bank access register.

2. The nonvolatile memory device of claim 1 , wherein the at least one serial data I/O comprises a plurality of bi-directional serial data I/Os.

3. The nonvolatile memory device of claim 1 , wherein the serial port is compatible with a Serial Peripheral Interconnect standard.

4. The nonvolatile memory device of claim 1 , wherein the at least one parallel port is compatible with some LPDDR4 standard operations, but not LPDDR4 write operations.

5. The nonvolatile memory device of claim 1 , further including a command decoder configured to receive command and address data from the plurality command address inputs, to enable read accesses to an addressed bank in response to no more than two commands.

6. The nonvolatile memory device of claim 5 , wherein each command received on the at least one parallel port includes a first set of parallel bits input on a rising edge of an input clock and a second set of parallel bits input on an immediate subsequent rising edge of the input clock.

7. A method of operating a nonvolatile memory (NVM) device, comprising:
in response to read accesses to an addressed NVM bank received at a parallel port, enabling or not enabling the read accesses via the parallel port according to an access value for the addressed NVM bank;
in response to read or write accesses to an addressed NVM bank received at a serial port, enabling or not enabling the read or write accesses via the serial port according to the access value for the addressed NVM bank; wherein
when a NVM bank access value enables access via the serial port, the NVM bank access value does not enable access via the parallel port,
the serial port includes at least one serial clock input and at least one serial input/output configured to receive command, address and write data in synchronism with the at least one serial clock input, and
the parallel port includes a plurality of command address inputs configured to receive command and address data in parallel, and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal.

8. The method of claim 7 , wherein the read accesses received at the parallel port include read accesses formed of no more than two commands.

9. The method of claim 8 , wherein in response to receiving two consecutive second read accesses in series at the parallel port directed to two different NVM banks, enabling the data for the different NVM banks to be output on consecutive data clock transitions without interruption.

10. The method of claim 8 , wherein each command includes a first set of parallel bits input on a rising edge of an input clock and a second set of parallel bits input on an immediate subsequent rising edge of the input clock.

11. The method of claim 7 , further including, in response to enabling a read access via the parallel port to an addressed NVM bank, setting the NVM access value for the NVM bank to a value that disables access to the NVM bank by the serial port.

12. The method of claim 11 , wherein setting the NVM access value for the NVM bank includes writing a value to a configuration register of the NVM device.

13. The method of claim 7 , wherein in response to read accesses to a first addressed NVM bank received at the parallel port and a read or write access to a second addressed NVM bank received at the serial port, enabling accesses to both the first and second addressed NVM banks at the same time.

14. A system, comprising:
a processor device comprising
at least one processing core
a first interface,
a second interface; and

a nonvolatile memory (NVM) device that includes
a read/write port configured to receive command, address and write data,
a read only parallel port that includes a plurality of command address inputs configured to receive command and address data in parallel, and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal,
a plurality of banks, each comprising NVM cells, and
a bank access register configured to store access values for each bank, wherein each bank is accessible by the read/write port or the read only port based on the access value for the bank stored in the bank access register;

a first bus coupled between the first interface and the read/write port; and
a parallel bus coupled between the second interface and the read only parallel port.

15. The system of claim 14 , wherein the processor device comprises a plurality of cores configured to control different parts of an automobile.

16. The system of claim 14 , wherein the NVM device is configured to enable first accesses via the read only parallel port in response to a sequence of no more than two read commands.

17. The system of claim 14 , wherein:
the read only parallel port is compatible with a LPDDR4 standard; and
the read commands are not part of the LPDDR4 standard.

18. The system of claim 14 , wherein each command received on the read only parallel port include a first set of parallel bits input on a rising edge of an input clock and a second set of parallel bits input on an immediate subsequent rising edge of the input clock.

19. The system of claim 14 , wherein the first port is compatible with a Serial Peripheral Interface (SPI) standard.

Assignees

• Cypress Semiconductor Corp

Inventors

• Betser Yoram
• Zitlaw Cliff
• Rosner Stephan
• Danon Kobi
• Rochman Amir

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F2213/0004

  Parallel ports, e.g. centronics · CPC title

• G06F2213/0002

  Serial port, e.g. RS232C · CPC title

• G06F13/4234

  being a memory bus · CPC title