Functional completion when retrying a non-interruptible instruction in a bi-modal execution environment

Patent metadata

Field	Value
Publication number	US-11449367-B2
Application number	US-201916286987-A
Country	US
Kind code	B2
Filing date	Feb 27, 2019
Priority date	Feb 27, 2019
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

A method is provided that includes receiving, by a firmware from an originating software, an asynchronous request for an instruction of an algorithm for compression of data. The firmware operates on a first processor and the originating software operates on a second processor. The firmware issues a synchronous request to the first processor to cause the processor to execute the instruction synchronously. It is determined, by the firmware, whether an interrupt is received from the first processor with respect to the first processor executing the instruction. The firmware retries the issuance of the synchronous request each time the interrupt is received until a retry threshold is reached.

First claim

What is claimed is:

1. A method comprising:
receiving, by a firmware from an originating software, an asynchronous request for an instruction of an algorithm for compression of data, the firmware operating on a first processor, and the originating software operating on a second processor;
issuing, by the firmware, a synchronous request to the first processor to cause the first processor to execute the instruction synchronously, wherein, in an event the first processor executes the instruction synchronously to completion, no interrupt is received and a reply is returned with an indicator set to off to inform an operating system of the instruction being executed synchronously to completion;
determining, by the firmware, whether an interrupt is received from the first processor with respect to the first processor executing the instruction but not to completion, the interrupt consisting of a dedicated indication to the firmware in a case of an abort due to the interrupt being required to be taken in an event of a failure of the synchronous request, wherein the instruction cannot write out a resumable intermediate state in a case of the interrupt being received and each interrupt is hidden from the operating system;
retrying, by the firmware providing asynchronous logic, the issuance of the synchronous request each time the interrupt is received for a number of times until a retry threshold is reached;
returning, by the firmware, an asynchronous response to the operating system with the indicator set to on upon the retry threshold being reached,
wherein the indicator, responsive to the returned asynchronous response, indicates to the operating system that:
the originating software is designated to retry the instruction synchronously; and
the synchronous request is designated to work on retry despite the failure and to enable the originating software to execute a synchronous fallback path to ensure completion of the instruction; and
issuing the synchronous request to the originating software so as to guarantee forward progress and functional completion, and
wherein, by retrying in a synchronous execution mode, the operating system is resilient against pathological cases due to an ability to suspend on interruption and to resume from an intermediate state.

2. The method of claim 1 , wherein the originating software issues a request block, as the asynchronous request, for the instruction to the firmware.

3. The method of claim 1 , wherein the firmware returns an asynchronous response with the indicator set to off if the first processor completed the instruction.

4. The method of claim 3 , wherein the originating software does not issue the synchronous request.

5. The method of claim 1 , wherein not receiving the interrupt by the firmware from the first processor indicates that the first processor has executed the instruction to completion.

6. The method of claim 1 , wherein receiving the interrupt by the firmware from the first processor indicates that the first processor failed to execute the instruction to completion.

7. The method of claim 1 , wherein the firmware returns a request block, as the asynchronous response, to the originating software.

8. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a first processor or a second processor to perform operations comprising:
receiving, by a firmware from an originating software, an asynchronous request for an instruction of an algorithm for compression of data, the firmware operating on the first processor, and the originating software operating on the second processor;
issuing, by the firmware, a synchronous request to the first processor to cause the first processor to execute the instruction synchronously, wherein, in an event the first processor executes the instruction synchronously to completion, no interrupt is received and a reply is returned with an indicator set to off to inform an operating system of the instruction being executed synchronously to completion;
determining, by the firmware, whether an interrupt is received from the first processor with respect to the first processor executing the instruction but not to completion, the interrupt consisting of a dedicated indication to the firmware in a case of an abort due to the interrupt being required to be taken in an event of a failure of the synchronous request, wherein the instruction cannot write out a resumable intermediate state in a case of the interrupt being received and the interrupt is hidden from the operating system;
retrying, by the firmware providing asynchronous logic, the issuance of the synchronous request each time the interrupt is received for a number of times until a retry threshold is reached;
returning, by the firmware, an asynchronous response to the operating system with the indicator set to on upon the retry threshold being reached,
wherein the indicator, responsive to the returned asynchronous response, indicates to the operating system that:
the originating software is designated to retry the instruction synchronously; and
the synchronous request is designated to work on retry despite the failure and to enable the originating software to execute a synchronous fallback path to ensure completion of the instruction; and
issuing the synchronous request to the originating software so as to guarantee forward progress and functional completion, and
wherein, by retrying in a synchronous execution mode, the operating system is resilient against pathological cases due to an ability to suspend on interruption and to resume from an intermediate state.

9. The computer program product of claim 8 , wherein in an operating system issues a request block, as the asynchronous request, for the instruction to the firmware.

10. The computer program product of claim 8 , wherein the firmware returns an asynchronous response with the indicator set to off if the first processor completed the instruction.

11. The computer program product of claim 8 , wherein the originating software does not issue the synchronous request.

12. The computer program product of claim 8 , wherein not receiving the interrupt by the firmware from the first processor indicates that the first processor has executed the instruction to completion.

13. The computer program product of claim 8 , wherein receiving the interrupt by the firmware from the first processor indicates that the first processor failed to execute the instruction to completion.

14. The computer program product of claim 8 , wherein the firmware returns a request block, as the asynchronous response, to the originating software.

15. A system comprising:
a first processor comprising firmware thereon, the firmware in communication with an originating software executing on a second processor, the system executable to perform operations comprising:
receiving, by a firmware from the originating software, an asynchronous request for an instruction of an algorithm for compression of data;
issuing, by the firmware, a synchronous request to the first processor to cause the first processor to execute the instruction synchronously, wherein, in an event the first processor executes the instruction synchronously to completion, no interrupt is received and a reply is returned with an indicator set to off to inform an operating system of the instruction being executed synchronously to completion;
determining, by the firmware, whether an interrupt is received from the first processor with respect to the first processor executing the instruction but not to completio

Assignees

• IBM

Inventors

• Klein Matthias
• Weishaupt Simon
• Sofia Anthony Thomas
• Bradbury Jonathan D
• Farrell Mark S
• Amin Mahmoud
• Slegel Timothy

Classifications

• G06F9/4818

  Priority circuits therefor · CPC title

• G06F9/54

  Interprogram communication · CPC title

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title

• G06F9/52 Primary

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title