High speed processing of financial information using FPGA devices

US9916622B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9916622-B2
Application numberUS-201414181949-A
CountryUS
Kind codeB2
Filing dateFeb 17, 2014
Priority dateJun 19, 2006
Publication dateMar 13, 2018
Grant dateMar 13, 2018

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Abstract

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A high speed apparatus and method for processing a plurality of financial market data messages are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to map the symbols present in the financial market data messages to another symbology.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus for processing streaming financial market data, the apparatus comprising: a computer system, the computer system comprising a reconfigurable logic device, a symbol index memory, and a processor; wherein the processor, the reconfigurable logic device, and the symbol index memory are configured to cooperate with each other to process the streaming financial market data; wherein the symbol index memory is configured to store a plurality of record keys, each record key corresponding to a financial instrument and identifying a memory address for data about the corresponding financial instrument; and wherein the processor is configured to (1) execute an operating system that includes a user space for a user mode and a kernel space for a kernel mode, (2) receive a feed of streaming financial market data through a network protocol stack, wherein the streaming financial market data comprises a plurality of financial market data messages, (3) use shared memory that is mapped into the kernel space and the user space to store financial market data within the financial market data messages while the financial market data messages are being processed by the processor, the stored financial market data including ticker symbol character strings and associated financial instrument price information, and (4) facilitate DMA transfers of the stored financial market data to the reconfigurable logic device from the shared memory; wherein the reconfigurable logic device is configured with a plurality of firmware application modules (FAMs) arranged in a pipeline, the FAMs including a symbol mapping FAM, the symbol mapping FAM configured to (1) process a plurality of the ticker symbol character strings within the streaming financial market data, the ticker symbol character strings configured to identify a plurality of financial instruments corresponding to the messages, (2) map the processed ticker symbol character strings to the record keys in the symbol index memory that correspond to the financial instruments identified by the processed ticker symbol character strings, and (3) output the mapped record keys; and wherein the reconfigurable logic device is further configured to (1) receive financial market data from the shared memory via the DMA transfers and (2) stream the received financial market data through the pipeline including the symbol mapping FAM. 2. The apparatus of claim 1 wherein the symbol mapping FAM is further configured to (1) process each ticker symbol character string via a transformation with respect to each ticker symbol character string, and (2) map the processed ticker symbol character strings to the record keys based on the transformations. 3. The apparatus of claim 2 wherein the transformation comprises a compression operation. 4. The apparatus of claim 2 wherein the transformation comprises an encoding operation. 5. The apparatus of claim 2 wherein the computer system further comprises: a record management memory, the record management memory configured to store data about the financial instruments identified by the ticker symbol character strings in memory addresses corresponding to the record keys, the financial instrument data comprising a plurality of pointers to a plurality of records for the financial instruments identified by the ticker symbol character strings; and wherein the FAMs further include a FAM downstream from the symbol mapping FAM, the downstream FAM configured to (1) receive the mapped record keys, and (2) retrieve a plurality of the pointers from the record management memory based on the mapped record keys. 6. The apparatus of claim 5 wherein the computer system further comprises: a record storage memory, the record storage memory configured to store the financial instrument records in memory addresses corresponding to the pointers in the record management memory; and wherein the downstream FAM is further configured to (1) retrieve a plurality of financial instrument records from the record storage memory based on the retrieved pointers, and (2) update the retrieved financial instrument records based on financial market data within the financial market data messages. 7. The apparatus of claim 6 wherein the symbol mapping FAM and the downstream FAM are configured to operate together simultaneously in a pipelined fashion such that the symbol mapping FAM is configured to operate with respect to a first financial market data message while the downstream FAM operates with respect to a second financial market data message. 8. The apparatus of claim 7 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA), and wherein the symbol mapping FAM and the downstream FAM are configured to operate together simultaneously in the pipelined fashion at hardware processing speeds. 9. The apparatus of claim 5 wherein the symbol index memory comprises a plurality N of the record keys, wherein N represents how many different unique financial instruments are supported by the record management memory, and wherein each record key comprises a binary value having a size of M bits, wherein M=log 2 (N). 10. The apparatus of claim 5 wherein the symbol index memory is separate from the record management memory. 11. The apparatus of claim 2 wherein the symbol index memory is internal to the reconfigurable logic device. 12. The apparatus of claim 2 wherein the symbol index memory comprises a memory device external from the reconfigurable logic device. 13. An apparatus for processing streaming financial market data, the apparatus comprising: a computer system, the computer system comprising a reconfigurable logic device and a processor; wherein the processor and the reconfigurable logic device are configured to cooperate with each other to process the streaming financial market data; wherein the processor is configured to (1) execute an operating system that includes a user space for a user mode and a kernel space for a kernel mode, (2) receive a feed of streaming financial market data messages through a network protocol stack, (3) use shared memory that is mapped into the kernel space and the user space to store financial market data within the financial market data messages while the financial market data messages are being processed by the processor, the stored financial market data including ticker symbol character strings and associated financial instrument price information, and (4) facilitate DMA transfers of the stored financial market data to the reconfigurable logic device from the shared memory; wherein the reconfigurable logic device is configured to (1) process a ticker symbol character string within streaming financial market data, wherein the ticker symbol character string representative of ticker symbol for a subject financial instrument, wherein the ticker symbol character string is member of a set of a plurality N of different ticker symbol character strings corresponding to N different financial instruments, (2) map the processed ticker symbol character string to a binary value within a set of a plurality N of different binary values, wherein each binary value in the set of N different binary values has a size of M bits and is representative of a different financial instrument, wherein M=log 2 (N), (3) use the mapped binary value as a unique identifier for the subject financial instrument with regard to the streaming financial market data, and (4) repeat the process, map, and use operations for a plurality of ticker symbol character strings within streaming financial market data for a plurality of financial instruments as the streaming financial market data streams through t

Assignees

Inventors

Classifications

  • Asset management; Financial planning or analysis · CPC title

  • Finance; Insurance; Tax strategies; Processing of corporate or income taxes · CPC title

  • G06Q40/04Primary

    Trading; Exchange, e.g. stocks, commodities, derivatives or currency exchange · CPC title

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Frequently asked questions

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What does patent US9916622B2 cover?
A high speed apparatus and method for processing a plurality of financial market data messages are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to map the symbols present in the financial market data messages to another symbology.
Who is the assignee on this patent?
Ip Reservoir Llc
What technology area does this patent fall under?
Primary CPC classification G06Q40/04. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 13 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).