Array substrate with light shielding metal portions and manufacturing method thereof, display device

Patent metadata

Field	Value
Publication number	US-11448929-B2
Application number	US-201916606895-A
Country	US
Kind code	B2
Filing date	May 16, 2019
Priority date	Jun 22, 2018
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate; a plurality of gate lines on a side of the base substrate; a plurality of data lines on a side of the plurality of gate lines away from the base substrate and intersecting with the plurality of gate lines; and a plurality of light shielding metal portions between the base substrate and each of the plurality of gate lines; respective one of the gate lines includes a plurality of gate line sub-segments separated by the plurality of data lines, respectively, every two adjacent gate line sub-segments in the respective one of the gate lines correspond to one of the light shielding metal portions, and the every two adjacent gate line sub-segments are connected in series through the one of the light shielding metal portions.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate;
a plurality of gate lines, disposed on a side of the base substrate;
a plurality of data lines, disposed on a side of the plurality of gate lines away from the base substrate and intersecting with the plurality of gate lines;
a plurality of light shielding metal portions, disposed between the base substrate and each of the plurality of gate lines, respectively,
wherein a respective one of the gate lines comprises a plurality of gate line sub-segments separated by the plurality of data lines, respectively, every two adjacent gate line sub-segments in the respective one of the gate lines are spaced apart from each other and correspond to one of the light shielding metal portions, and the every two adjacent gate line sub-segments in the respective one of the gate lines are connected in series through the one of the light shielding metal portions;
a plurality of gate line floating segments, disposed between the base substrate and each of the data lines;
a plurality of pixel units arranged in an array, wherein a respective one of the pixel units comprises a thin film transistor, and the thin film transistor is disposed on the base substrate;
wherein a respective gate line floating segment is disposed between the every two adjacent gate line sub-segments in the respective one of the gate lines, and is insulated from corresponding two gate line sub-segments in a same layer as the respective gate line floating segment;
the thin film transistor further comprises an active layer between a respective gate line and a respective light shielding metal portion, and insulated from the respective gate line and the respective light shielding metal portion, respectively; and
the active layer is U-shaped, and one branch of the active layer that is U-shaped intersects with the respective gate line floating segment.

2. The array substrate according to claim 1 , wherein
an orthographic projection of the respective one of the gate line sub-segments on the base substrate partially overlaps with an orthographic projection portion of a corresponding light shielding metal portion on the base substrate; and
an orthographic projection of a respective one of the light shielding metal portions on the base substrate intersects with an orthographic projection of a respective data line used to form corresponding gate line sub-segments by separation on the base substrate.

3. The array substrate according to claim 1 ,
wherein a source-drain electrode of the thin film transistor is disposed in a same layer as the plurality of data lines; and gate electrodes of thin film transistors of pixel units in one row correspond to one of the plurality of gate lines.

4. The array substrate according to claim 1 , wherein an orthographic projection of the active layer on the base substrate intersects with an orthographic projection of a respective gate line floating segment on the base substrate.

5. The array substrate according to claim 4 , wherein the orthographic projection of the active layer on the base substrate partially overlaps with an orthographic projection of a respective data line used to form corresponding gate line sub-segments by separation on the base substrate.

6. The array substrate according to claim 1 , wherein an orthographic projection of the active layer on the base substrate partially overlaps with an orthographic projection of a respective data line used to form corresponding gate line sub-segments by separation on the base substrate.

7. The array substrate according to claim 1 , wherein the thin film transistor uses the one of the light shielding metal portions connecting the every two adjacent gate line sub-segments in the respective one of the gate lines as a gate electrode of the thin film transistor.

8. The array substrate according to claim 1 , wherein another branch of the active layer that is U-shaped intersects with one of the every two adjacent gate line sub-segments in the respective one of the gate lines.

9. The array substrate according to claim 8 , wherein a gate electrode of the thin film transistor is disposed in a same layer as the plurality of gate lines.

10. The array substrate according to claim 1 , further comprising:
an interlayer insulating layer, disposed between the plurality of gate lines and the plurality of data lines.

11. The array substrate according to claim 1 , further comprising:
at least one of a gate insulating layer and a buffer layer, and the at least one of the gate insulating layer and the buffer layer is disposed between a respective gate line sub-segment of the gate lines and a corresponding light shielding metal portion.

12. The array substrate according to claim 1 , wherein a material for manufacturing the plurality of light shielding metal portions is same as a material for manufacturing the plurality of gate lines.

13. A display device, comprising the array substrate according to claim 1 .

14. A manufacturing method of an array substrate, comprising:
providing a base substrate, and forming a plurality of light shielding metal portions on a side of the base substrate;
forming a plurality of gate lines on a side of the plurality of light shielding metal portions away from the base substrate, wherein a respective one of the gate lines comprises a plurality of gate line sub-segments, every two adjacent gate line sub-segments in the respective one of the gate lines correspond to one of the light shielding metal portions, and the every two adjacent gate line sub-segments in the respective one of the gate lines are spaced apart from each other and are connected in series through the one of the light shielding metal portions;
forming a plurality of data lines on a side of the plurality of gate lines away from the plurality of light shielding metal portions, wherein the every two adjacent gate line sub-segments are located at two sides of a respective data line, respectively;
forming a plurality of gate line floating segments between the base substrate and each of the data lines;
forming a plurality of pixel units arranged in an array, wherein a respective one of the pixel units comprises a thin film transistor, and the thin film transistor is disposed on the base substrate;
wherein a respective gate line floating segment is between the every two adjacent gate line sub-segments in the respective one of the gate lines, and is insulated from corresponding two gate line sub-segments in a same layer as the respective gate line floating segment;
the thin film transistor further comprises an active layer between a respective gate line and a respective light shielding metal portion, and insulated from the respective gate line and the respective light shielding metal portion, respectively; and
the active layer is U-shaped, and one branch of the active layer that is U-shaped intersects with the respective gate line floating segment.

15. The manufacturing method of the array substrate according to claim 14 , wherein the forming the plurality of gate lines on a side of the plurality of light shielding metal portions away from the base substrate, comprises:
forming a buffer layer and a gate insulating layer sequentially on surfaces of the plurality of light shielding metal portions away from the base substrate, and forming a plurality of via holes in the buffer layer and the gate insulating layer by a patterning process; and
forming the plurality of gate lines on a surface of the gate insulating layer away from the plurality of light shielding metal portions, gate line sub-segments in the respective one of the gate lines b

Assignees

• Ordos Yuansheng Optoelectronics Co Ltd
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Yao Lei
• Shi Dawei
• Wang Wentao
• Yang Lu
• Xu Haifeng
• Yan Lei
• Wang Jinfeng
• Xue Jinjin
• Yan Fang
• Si Xiaowen
• Hou Lin
• Guo Zhixuan
• Li Yuanbo
• Li Xiaofang

Classifications

• G02F1/13606 Primary

  having means for reducing parasitic capacitance · CPC title

• G02F1/136218 Primary

  Shield electrodes · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/13629

  Multilayer wirings · CPC title

• G02F1/136295

  Materials; Compositions; Manufacture processes · CPC title