LTPS array substrate

Patent metadata

Field	Value
Publication number	US-9620536-B2
Application number	US-201414426464-A
Country	US
Kind code	B2
Filing date	Dec 29, 2014
Priority date	Dec 16, 2014
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

An LTPS array substrate includes a plurality of LTPS thin-film transistors and a bottom transparent conductive layer, a protective layer, and a top transparent conductive layer. Each LTPS thin-film transistor includes a substrate, a patternized light shield layer, a buffering layer, a patternized poly-silicon layer, a gate insulation layer, a gate line, and a common electrode line, an insulation layer, a drain and a source, and a planarization layer that are formed to sequentially stack on each other. The light shield layer covers the scan line and the source/drain. A patternized third metal layer is between the bottom transparent conductive layer and the protective layer and includes a first zone and a second zone intersecting the first zone. The first zone shields the source line. A portion of the second zone overlaps a side portion of the light shield layer that is close to the source/drain electrode.

First claim

What is claimed is:

1. A low temperature poly-silicon (LTPS) array substrate, comprising a plurality of LTPS thin-film transistors, a bottom transparent conductive layer, a protective layer formed on the bottom transparent conductive layer, and a top transparent conductive layer formed on the protective layer, each of the LTPS thin-film transistors comprising a substrate;
a patternized light shield layer formed on the substrate;
a buffering layer formed on the substrate and the patternized light shield layer;
a patternized poly-silicon layer formed on the buffering layer;
a gate insulation layer formed on the patternized poly-silicon layer and the buffering layer;
a first metal layer formed on the gate insulation layer, the first metal layer being patternized to form a scan line, the scan line having an orthogonal projection cast on the light shield layer;
an insulation layer formed on the patternized first metal layer;
a second metal layer formed on the insulation layer, the second metal layer being patternized to form a data line and a source/drain electrode, the data line and the scan line being arranged to intersect each other;
a planarization layer formed on the insulation layer and the patternized second metal layer, the bottom transparent conductive layer being formed on the planarization layer, wherein:
the patternized light shield layer covers the scan line and the source/drain electrode, a patternized third metal layer being formed between the bottom transparent conductive layer and the protective layer, the patternized third metal layer comprises a first zone and a second zone arranged to intersect the first zone, the first zone shielding the data line, the second zone having a portion overlapping a side portion of the light shield layer that is close to the source/drain electrode so as to shield, in combination with the light shield layer, the source/drain electrode and a portion of the scan line.

2. The LTPS array substrate as claimed in claim 1 , wherein the patternized third metal layer is a touch sensing electrode layer.

3. The LTPS array substrate as claimed in claim 1 , wherein the scan line comprises an extension zone extending therefrom and covering a portion of the patternized poly-silicon layer, the extension zone being shielded by the light shield layer and the second zone.

4. The LTPS array substrate as claimed in claim 1 , wherein the second zone and the light shield layer are arranged to partly overlap so that the second zone and the light shield layer for a shielding zone in a widthwise direction, the widthwise direction is a direction extending from the scan line of the LTPS thin-film transistor toward the source/drain electrode.

5. The LTPS array substrate as claimed in claim 1 , wherein the patternized second metal layer is electrically connected through a via to the poly-silicon layer.

6. The LTPS array substrate as claimed in claim 1 , wherein the top transparent conductive layer is formed on the protective layer and is electrically connected through a via to the source/drain electrode.

7. The LTPS array substrate as claimed in claim 1 , wherein the gate insulation layer is made of one of silicon oxide, silicon nitride, and silicon oxynitride.

8. The LTPS array substrate as claimed in claim 1 , wherein the first metal layer and the second metal layer comprise materials that are electrically conductive materials of molybdenum/aluminum alloys and chromium metal.

9. The LTPS array substrate as claimed in claim 1 , wherein the bottom transparent conductive layer and the top transparent conductive layer are made of transparent conductive materials.

10. The LTPS array substrate as claimed in claim 1 , wherein the third metal layer has a grid configuration.

Assignees

• Shenzhen China Star Optoelect
• Shenzhen China Star Optoelect

Inventors

• Du Peng
• Hu Yutong

Classifications

• H10D86/00

  Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates · CPC title

• H01L27/12

  Electricity · mapped topic

• G02F2001/136231

  Physics · mapped topic

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• H01L29/458

  Electricity · mapped topic