Method and device for determining junction temperature of die of semiconductor power module

Patent metadata

Field	Value
Publication number	US-11448557-B2
Application number	US-201716064379-A
Country	US
Kind code	B2
Filing date	Jan 30, 2017
Priority date	Feb 18, 2016
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

A method for determining the junction temperature of at least one die of a semiconductor power module, the semiconductor power module being composed of plural dies connected in parallel and switching between conducting and non conductor states according to pattern cycles, the method comprises the steps of: disabling the conducting of the at least one die during at least a fraction of one switching cycle, applying a current limited voltage to the gate of the at least one die during a period of time of the cycle wherein the at least one die is not conducting, the resulting voltage excursion having a value that does not enable the die to be conducting, measuring the voltage at the gate of the die, deriving from the measured voltage a temperature variation of the junction of the at least one die or the temperature of the junction of the die.

First claim

The invention claimed is:

1. Method for determining the junction temperature of at least one die of a semiconductor power module, the semiconductor power module being composed of plural dies connected in parallel and switching between conducting and non conducting states according to pattern cycles, the method comprising:
setting the at least one die in a non-conducting state during at least a fraction of one switching cycle,
applying a current limited voltage to the gate of the at least one die during a period of time of the cycle wherein the at least one die is not conducting, the resulting voltage excursion having a value that does not enable the at least one die to be conducting,
measuring the voltage at the gate of the at least one die,
calculating a gate internal resistance based on the measured voltage, and
deriving from the gate internal resistance a temperature variation of the junction of the at least one die or the temperature of the junction of the at least one die,
wherein a sampling time for each voltage measurement used for calculating the gate internal resistance is limited to a time during which the at least one die is not enabled to be conducting.

2. Method according to claim 1 , wherein the gates of all the dies are connected together and all the dies are disabled during the same cycle, the current limited voltage is applied to the gates of all the dies during the period of time of the cycle wherein the dies are not conducting and the temperature variation or the temperature is the average temperature or average temperature variation of the junctions of the dies.

3. Method according to claim 2 , wherein the current of the applied voltage is comprised between 10 to 100 mA.

4. Method according to claim 1 , wherein the current of the applied voltage is comprised between 10 to 100 mA.

5. Method for determining the junction temperature of at least one die of a semiconductor power module, the semiconductor power module being composed of plural dies connected in parallel and switching between conducting and non conducting states according to pattern cycles, the method comprising:
setting the at least one die in a non-conducting state during at least a fraction of one switching cycle,
applying a current limited voltage to the gate of the at least one die during a period of time of the cycle wherein the at least one die is not conducting, the resulting voltage excursion having a value that does not enable the at least one die to be conducting,
measuring the voltage at the gate of the at least one die,
calculating a gate internal resistance based on the measured voltage, and
deriving from the gate internal resistance a temperature variation of the junction of the at least one die or the temperature of the junction of the at least one die, wherein the gate of each die is not connected through one node to the gates of the other dies and a single die is disabled during one cycle.

6. Method according to claim 5 , wherein the dies are disabled at different cycles based on a round robin basis.

7. Method according to claim 6 , wherein the current of the applied voltage is comprised between 10 to 100 mA.

8. Method according to claim 5 , wherein the current limited voltage to the gate of the die is applied after the commutation to the conducting state of the other dies is complete.

9. Method according to claim 8 , wherein the voltage at the gate of the die is measured at a time based on a characteristic of an analogue to digital converter used for digitizing measured voltage, the characteristic being determinative of a longest time-constant for stable measurement by the analogue to digital converter.

10. Method according to claim 9 , wherein the current of the applied voltage is comprised between 10 to 100 mA.

11. Method according to claim 8 , wherein the method comprises further interrupting the current limited voltage provided to the gate after the measurement.

12. Method according to claim 11 , wherein the current of the applied voltage is comprised between 10 to 100 mA.

13. Method according to claim 8 , wherein the current of the applied voltage is comprised between 10 to 100 mA.

14. Method according to claim 5 , wherein the voltage at the gate of the die is measured at a time based on a characteristic of an analogue to digital converter used for digitizing measured voltage, the characteristic being determinative of a longest time-constant for stable measurement by the analogue to digital converter.

15. Method according to claim 14 , wherein the current of the applied voltage is comprised between 10 to 100 mA.

16. Method according to claim 5 , wherein the method comprises further interrupting the current limited voltage provided to the gate after the measurement.

17. Method according to claim 16 , wherein the current of the applied voltage is comprised between 10 to 100 mA.

18. Method according to claim 5 , wherein the current of the applied voltage is comprised between 10 to 100 mA.

19. Device for determining the junction temperature of at least one die of a semiconductor power module, the semiconductor power module being composed of plural dies connected in parallel and switching between conducting and non conducting states according to pattern cycles, the device comprises: processing circuitry
to set the at least one die in a non-conducting state during at least a fraction of one switching cycle,
to apply a current limited voltage to the gate of the at least one die during a period of time of the cycle wherein the at least one die is not conducting, the applied current limited voltage having a voltage value that does not enable the at least one die to be conducting,
to measure the voltage at the gate of the at least one die,
to calculate a gate internal resistance based on the measured voltage,
to derive from the gate internal resistance a temperature variation of the junction of the at least one die or the temperature of the junction of the at least one die,
wherein a sampling time for each voltage measurement used for calculating the gate internal resistance is limited to a time during which the at least one die is not enabled to be conducting.

Assignees

• Mitsubishi Electric Corp

Inventors

• Ewanchuk Jeffrey
• Mollov Stefan
• Robinson Jonathan
• Brandelero Julio

Classifications

• G01K13/00

  Thermometers specially adapted for specific purposes · CPC title

• H03K17/145

  in field-effect transistor switches · CPC title

• G01K7/16 Primary

  using resistive elements · CPC title

• G01K2217/00

  Temperature measurement using electric or magnetic components already present in the system to be measured · CPC title

• H03K17/122

  in field-effect transistor switches · CPC title