Smooth transition of a power supply from a first mode, such as a pulse-frequency-modulation (pfm) mode, to a second mode, such as a pulse-width-modulation (pwm) mode
US-2015061626-A1 · Mar 5, 2015 · US
US2019013784A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2019013784-A1 |
| Application number | US-201715660717-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jul 26, 2017 |
| Priority date | Jul 10, 2017 |
| Publication date | Jan 10, 2019 |
| Grant date | — |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
System controller and method for providing at least an output voltage. For example, the system controller includes a first controller terminal configured to receive an input voltage. The input voltage is associated with an input-voltage magnitude. Additionally, the system controller includes a second controller terminal configured to receive a control voltage, and a third controller terminal configured to output an output voltage to a load. Moreover, the system controller includes a supply voltage generator configured to receive the input voltage from the first controller terminal and generate a supply voltage. The supply voltage is associated with a supply voltage magnitude. Also, the system controller includes a ramp voltage generator configured to receive the supply voltage and generate a ramp voltage.
Opening claim text (preview).
What is claimed is: 1 . A system controller for providing at least an output voltage, the system controller comprising: a first controller terminal configured to receive an input voltage, the input voltage being associated with an input-voltage magnitude; a second controller terminal configured to receive a control voltage; a third controller terminal configured to output an output voltage to a load; a supply voltage generator configured to receive the input voltage from the first controller terminal and generate a supply voltage, the supply voltage being associated with a supply voltage magnitude; and a ramp voltage generator configured to receive the supply voltage and generate a ramp voltage; wherein, if the control voltage is at a first logic level, the ramp voltage increases from zero to the supply voltage magnitude at a first rate of change during a first time duration; and the output voltage increases from zero to the input-voltage magnitude at a second rate of change during a second time duration; wherein the second rate of change is equal to the first rate of change multiplied by a predetermined constant. 2 . The system controller of claim 1 , and further comprising a fourth controller terminal biased to a predetermined voltage. 3 . The system controller of claim 2 , wherein, if the control voltage is at a second logic level, the output voltage is equal to the predetermined voltage. 4 . The system controller of claim 3 wherein the predetermined voltage is a ground voltage. 5 . The system controller of claim 1 wherein the second rate of change does not change with the load. 6 . The system controller of claim 5 wherein the load includes a resistive load. 7 . The system controller of claim 5 wherein the load includes a capacitive load. 8 . The system controller of claim 7 wherein the load further includes a resistive load. 9 . A system controller for providing at least an output voltage, the system controller comprising: a first controller terminal configured to receive an input voltage; a second controller terminal configured to receive a control voltage; a third controller terminal configured to output an output voltage; a fourth controller terminal biased to a predetermined voltage; a transistor including a gate terminal, a drain terminal and a source terminal, the drain terminal being connected to the first controller terminal, the source terminal being connected to the third controller terminal; a first resistor including a first resistor terminal and a second resistor terminal, the first resistor terminal being connected to the third controller terminal; a second resistor including a third resistor terminal and a fourth resistor terminal, the third resistor terminal being connected to the second resistor terminal, the fourth resistor terminal being connected to the fourth controller terminal; a third resistor including a fifth resistor terminal and a sixth resistor terminal, the fifth resistor terminal being configured to receive a first voltage related to the output voltage, the sixth resistor terminal being connected to the gate terminal of the transistor; a ramp voltage generator configured to generate a ramp voltage; a transconductance operational amplifier including a first amplifier terminal, a second amplifier terminal and a third amplifier terminal, the first amplifier terminal being configured to receive a second voltage from the second resistor terminal and the third resistor terminal, the second amplifier terminal being configured to receive the ramp voltage from the ramp voltage generator, the third amplifier terminal being connected to the sixth resistor terminal and the gate terminal of the transistor. 10 . The system controller of claim 9 , and further comprising a charge pump configured to receive the control voltage and the output voltage and generate the first voltage. 11 . The system controller of claim 10 wherein the charge pump is further configured to: in response to the control voltage being at a first logic level, generate the first voltage equal to a sum of the output voltage and a predetermined voltage change, the predetermined voltage change being larger than zero; and in response to the control voltage being at a second logic level, generate the first voltage equal to the output voltage. 12 . The system controller of claim 9 wherein the predetermined voltage is a ground voltage. 13 . The system controller of claim 12 wherein the second voltage is equal to the output voltage multiplied by a predetermined constant determined by at least a first resistance of the first resistor and a second resistance of the second resistor. 14 . The system controller of claim 9 wherein the transconductance operational amplifier is configured to, in response to the second voltage being larger than the ramp voltage, generate an amplified current flowing into the transconductance operational amplifier through the third amplifier terminal. 15 . The system controller of claim 14 wherein the transconductance operational amplifier is further configured to, in response to the second voltage being smaller than the ramp voltage, generate the amplified current flowing out of the transconductance operational amplifier through the third amplifier terminal. 16 . A system controller for providing at least an output current, the system controller comprising: a first controller terminal configured to receive an input voltage; a second controller terminal configured to output an output current; a first transistor including a first gate terminal, a first drain terminal and a first source terminal, the first drain terminal being configured to receive the input voltage, the first source terminal being connected to the second controller terminal; a second transistor including a second gate terminal, a second drain terminal and a second source terminal, the second source terminal being connected to the second controller terminal; a first resistor including a first resistor terminal and a second resistor terminal, the first resistor terminal being configured to receive the input voltage, the second resistor terminal being associated with a first voltage and connected to the second drain terminal; a second resistor including a third resistor terminal and a fourth resistor terminal, the third resistor terminal being configured to receive a second voltage, the fourth resistor terminal being connected to the first gate terminal of the first transistor and the second gate terminal of the second transistor; a transconductance operational amplifier including a first amplifier terminal, a second amplifier terminal and a third amplifier terminal, the third amplifier terminal being connected to the fourth resistor terminal, the first gate terminal of the first transistor, and the second gate terminal of the second transistor; wherein the transconductance operational amplifier is configured to: generate an amplified current based on at least information associated with the input voltage and the first voltage; and in response to the input voltage minus the first voltage being larger than a predetermined offset voltage, generate the amplified current flowing into the transconductance operational amplifier through the third amplifier terminal. 17 . The system controller of claim 16 wherein the transconductance operational amplifier is further configured to, in response to the input voltage minus the first voltage being smaller than the predetermined offset voltage, generate the amplified current flowing out of th
Soft switching · CPC title
with a plurality of power processing stages connected in parallel · CPC title
Push-pull amplifiers; Phase-splitters therefor (duplicated single-ended push-pull arrangements or phase-splitters therefor H03F3/30) · CPC title
using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title
in transistor amplifiers · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.