Driver assisted ESD protection apparatus and method

US11444445B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11444445-B2
Application numberUS-202017125824-A
CountryUS
Kind codeB2
Filing dateDec 17, 2020
Priority dateJun 11, 2020
Publication dateSep 13, 2022
Grant dateSep 13, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Analog Front End (AFE) driver or transmitter is used for ESD protection of an input-output (IO) pin, thus reducing ESD diode count and subsequently lowering the pad capacitance to achieve high performance in IO circuits like double data rate (DDR) IO, PCI Express (Peripheral Component Interconnect Express), etc. The channel of active devices that constitute AFE driver are used to connect an IO pad to discharge the ESD current to ground, thus providing an alternative path to ESD current and subsequently reducing the ESD diode count. An additional p-type device (Driver Path Enabler (DPE)) is coupled between the IO pad and a gate terminal of the AFE driver. This additional p-type device triggers the channel of the AFE driver. This p-type device is controlled by an RC based structure which cuts the p-type device off during regular operations when power is ramped-up.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus comprising: a pad; a driver coupled to the pad, wherein the driver comprises a pull up device coupled in a series path with a pull down device, the pull up device is coupled to a power supply rail, the pull down device is coupled to ground and the pad is coupled to a point in the series path, the point is between the pull up device and the pull down device; and a circuit to couple the pad to a gate of the pull down device when a voltage rise occurs on the pad due to an Electro Static Discharge (ESD) event, wherein the voltage rise is to turn on the pull down device to ground the pad via the pull down device. 2. The apparatus of claim 1 , wherein the circuit is to turn off the pull down device when the ESD event completes. 3. The apparatus of claim 1 , further comprising a timer coupled to the pad via the power supply rail, wherein the timer is to output a signal indicating a duration of time the circuit is to turn on the pull down device when the ESD event occurs on the pad. 4. The apparatus of claim 3 , wherein: the circuit comprises a first p-type device coupled in a path between the gate of the pull down device of the driver and the pad; and a gate of the first p-type device is coupled to the timer to receive the signal. 5. The apparatus of claim 3 , further comprising a clamp circuit coupled to the timer and to the power supply rail, wherein the clamp circuit is to turn on in response to the signal during the ESD event, to provide a ground path for the pad via the power supply rail. 6. The apparatus of claim 1 , wherein the circuit is to couple the pad to the gate of the pull down device via the point which is between the pull up device and the pull down device. 7. The apparatus of claim 1 , wherein the pull down device is an n-type device. 8. The apparatus of claim 1 , wherein the ESD event occurs when there is no power supply to the power supply rail. 9. The apparatus of claim 1 , wherein: the circuit is to couple the pad to a gate of the pull up device during the ESD event; and the pull up device is a p-type device. 10. The apparatus of claim 1 , wherein the circuit comprises a p-type device to couple the pad to the gate of the pull down device. 11. The apparatus of claim 1 , wherein: the pull down device and the pull up device operate as device drivers during a normal, non-ESD mode of the driver. 12. The apparatus of claim 4 , wherein: the first p-type device is to turn off in response to the timer when the ESD event completes. 13. An apparatus, comprising: a pad; a driver coupled to the pad, wherein the driver comprises a pull up device coupled in a series path with a pull down device, the pull up device is coupled to a power supply rail, the pull down device is coupled to ground and the pad is coupled to a point in the series path, the point is between the pull up device and the pull down device; and a circuit to couple the pad to a gate of the pull up device when a voltage drop occurs on the pad due to an Electro Static Discharge (ESD) event, wherein the voltage drop is to turn on the pull up device to provide a ground path for the pad, the ground path comprises the pull up device and the power supply rail. 14. The apparatus of claim 13 , further comprising a clamp circuit coupled to the power supply rail, wherein the ground path comprises the clamp circuit. 15. The apparatus of claim 13 , wherein the pull up device comprises a p-type device. 16. The apparatus of claim 13 , further comprising a timer coupled to the pad via the power supply rail, wherein the timer is to output a signal indicating a duration of time the circuit is to turn on the pull up device when the ESD event occurs. 17. The apparatus of claim 16 , wherein: the circuit comprises a first p-type device coupled in a path between the gate of the pull up device of the driver and the pad; and a gate of the first p-type device is coupled to the timer to receive the signal.

Assignees

Inventors

Classifications

  • H02H3/08Primary

    responsive to excess current (responsive to abnormal temperature caused by excess current H02H5/04) · CPC title

  • H02H9/046Primary

    responsive to excess voltage appearing at terminals of integrated circuits · CPC title

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Frequently asked questions

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What does patent US11444445B2 cover?
Analog Front End (AFE) driver or transmitter is used for ESD protection of an input-output (IO) pin, thus reducing ESD diode count and subsequently lowering the pad capacitance to achieve high performance in IO circuits like double data rate (DDR) IO, PCI Express (Peripheral Component Interconnect Express), etc. The channel of active devices that constitute AFE driver are used to connect an IO …
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H02H3/08. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 13 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).