Electrostatic discharge clamp circuit for ultra-low power applications

Patent metadata

Field	Value
Publication number	US-9716381-B2
Application number	US-201414491017-A
Country	US
Kind code	B2
Filing date	Sep 19, 2014
Priority date	Sep 20, 2013
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

An electrostatic discharge clamp circuit is provided for low power applications. The clamp circuit includes: a detection circuit, a bias circuit and a shunting circuit having at least one shunt transistor. The detection circuit is configured to detect an occurrence of an electrostatic charge on a power supply node and trigger discharge of the electrostatic charge through the shunting circuit. The bias circuit is coupled between the detection circuit and the shunting circuit and applies a bias voltage to the gate terminal of the shunt transistor. During an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially equal to the supply voltage; whereas, during the absence of an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially half of the supply voltage.

First claim

What is claimed is:

1. An electrostatic discharge clamp circuit for low power applications, comprising:
a shunting circuit electrically coupled between a supply voltage and ground and comprised of at least one shunt transistor;
a detection circuit electrically coupled between the supply voltage and ground, the detection circuit is configured to detect an occurrence of an electrostatic charge on a power supply node and trigger discharge of the electrostatic charge through the shunt transistor; and
a bias circuit electrically coupled between the detection circuit and the shunting circuit and the bias circuit applies a bias voltage to the gate terminal of the shunt transistor and to body of the shunt transistor during absence of an electrostatic discharge event, where the bias voltage is substantially half of the supply voltage.

2. The clamp circuit of claim 1 further comprises a capacitor electrically coupled between the supply voltage and a detection node, where the detection circuit is electrically connected via the detection node to the bias circuit.

3. The clamp circuit of claim 1 wherein the detection circuit is implemented by a static CMOS inverter having an input coupled to an RC filter.

4. The clamp circuit of claim 3 wherein the RC filter employs a metal-insulator-metal capacitor.

5. The clamp circuit of claim 1 wherein the shunt circuit is comprised of a first metal-oxide-semiconductor field-effect transistor (MOSFET) and a second MOSFET, where a drain terminal of the first MOSFET is coupled to the supply voltage, a source terminal of the first MOSFET is coupled to a drain terminal of the second MOSFET, and a source terminal of the second MOSFET is coupled to ground.

6. The clamp circuit of claim 5 wherein the first MOSFET has a gate terminal sized the same as the gate terminal of the second MOSFET and the first MOSFET having the same type of charge carrier as the second MOSFET.

7. The clamp circuit of claim 5 wherein the bias circuit applies a bias voltage a gate terminal of the first MOSFET, where the bias voltage is substantially equal to the supply voltage during an electrostatic discharge event and the bias voltage is substantially half of the supply voltage during absence of an electrostatic discharge event.

8. The clamp circuit of claim 7 wherein the bias circuit is comprised of a third MOSFET coupled in series with a fourth MOSFET, where a source terminal of the third MOSFET is coupled to the supply voltage, a drain terminal of the third MOSFET is coupled at a bias node to a source terminal of the fourth MOSFET, a drain terminal of the fourth MOSFET is coupled to the drain terminal of the second MOSFET, and the bias node is coupled to the gate terminal of the first MOSFET.

9. The clamp circuit of claim 8 wherein the gate terminal of the third MOSFET is coupled via an inverter to the detection node and the gate terminal of the fourth MOSFET is coupled to the detection node.

10. The clamp circuit of claim 8 further comprises a capacitor electrically coupled between the supply voltage and the bias node.

11. The clamp circuit of claim 7 wherein the bias circuit is comprised of an even number of diode-connected MOSFETs coupled in series, where one half of the diode-connected MOSFETs are coupled at a bias node to the other half of the diode-connected MOSFETs and the bias node is coupled to the gate terminals of the first MOSFET.

12. The clamp circuit of claim 11 wherein the bias circuit further includes a driving MOSFET with a source terminal coupled to the supply voltage, the drain terminal coupled to the bias node and a gate terminal coupled via an inverter to the detection node.

13. The clamp circuit of claim 11 wherein the gate terminals of the diode-connected MOSFETs are sized to create a leakage current that is larger than subthreshold leakage of driving MOSFET and larger than gate leakage of the first MOSFET.

14. A clamp circuit for low power applications, comprising:
a shunting circuit comprised of two shunt transistors electrically coupled between a supply voltage and ground and in series to each other;
a detection circuit electrically coupled between the supply voltage and ground, wherein the detection circuit is electrically connected via a detection node to the shunting circuit and configured to discharge an electrostatic charge through the two shunt transistors;
a capacitor electrically coupled between the supply voltage and the detection node; and
a bias circuit electrically coupled to a gate terminal of a first of the two shunt transistors and applies a bias voltage to the gate terminal during absence of an electrostatic discharge event, where the bias circuit is comprised of a first p-type metal-oxide-semiconductor field-effect transistor (MOSFET) coupled in series with a p-type second MOSFET, where a source terminal of the first MOSFET is coupled to the supply voltage, a drain terminal of the first MOSFET is coupled at a bias node to a source terminal of the second MOSFET, a drain terminal of the first MOSFET is coupled to a node interconnecting the two shunt transistors, and the bias node is coupled to the gate terminal of the first of the two shunt transistors.

15. The clamp circuit of claim 14 wherein the gate terminal of the first MOSFET is coupled via an inverter to the detection node and the gate terminal of the second MOSFET is coupled to the detection node.

16. The clamp circuit of claim 14 wherein the two shunting transistors have gate terminals sized the same and have the same type of charge carrier.

17. The clamp circuit of claim 14 wherein the bias circuit applies a bias voltage a gate terminal of the first of the two shunting transistors, where the bias voltage is substantially equal to the supply voltage during an electrostatic discharge event and the bias voltage is substantially half of the supply voltage during absence of an electrostatic discharge event.

18. The clamp circuit of claim 14 further comprises a capacitor electrically coupled between the supply voltage and the bias node.

19. The clamp circuit of claim 14 wherein the detection circuit is implemented by a static CMOS inverter having an input coupled to an RC filter.

20. The clamp circuit of claim 19 wherein the RC filter employs a metal-insulator-metal capacitor.

21. A clamp circuit for low power applications, comprising:
a shunting circuit comprised of two shunt transistors electrically coupled between a supply voltage and ground and in series to each other;
a detection circuit electrically coupled between the supply voltage and ground, wherein the detection circuit is electrically connected via a detection node to the shunting circuit and configured to discharge an electrostatic charge through the two shunt transistors;
a capacitor electrically coupled between the supply voltage and the detection node; and
a bias circuit electrically coupled to a gate terminal of a first of the two shunt transistors and applies a bias voltage to the gate terminal and to body of the first of the two shunt transistors during absence of an electrostatic discharge event, where the bias circuit is comprised of an even number of diode-connected n-type MOSFETs coupled in series, where one half of the diode-connected MOSFETs are coupled at a bias node to the other half of the diode-connected MOSFETs and the bias node is coupled to the gate terminals of the first MOSFET.

22. The clamp circuit of claim 21 wherein the bias circuit applies a bias voltage a gate terminal of the first

Assignees

• Univ Michigan Regents

Inventors

• Chen Yen-Po
• Lee Yoonmyung
• Sim Jae-Yoon
• Alioto Massimo
• Sylvester Dennis
• Blaauw David

Classifications

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H02H1/04

  Arrangements for preventing response to transient abnormal conditions, e.g. to lightning {or to short duration over voltage or oscillations; Damping the influence of DC component by short circuits in AC networks} · CPC title

• H02H9/04

  responsive to excess voltage (lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T) · CPC title