Display panel and preparation method, detection method and display device thereof

Patent metadata

Field	Value
Publication number	US-11444142-B2
Application number	US-202016771646-A
Country	US
Kind code	B2
Filing date	Jan 6, 2020
Priority date	Jun 13, 2019
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

The present application discloses embodiments of a display panel, a preparation method thereof, a detection method thereof, and a display device for improving an accuracy of detecting electrical properties of transistors. In one embodiment, a display panel may include a display area including a plurality of pixels and a non-display area surrounding the display area, wherein each of the plurality of pixels may include a display pixel circuit, and the non-display area may include one or more test pixel circuits, each of the one or more test pixel circuits having an equivalent circuit structure to the display pixel circuit, where the one or more test pixel circuits may include a plurality of transistors, and electrodes of at least one of the plurality of transistors may be respectively conductively coupled to different test pads.

First claim

The invention claimed is:

1. A display panel, comprising:
a display area comprising a plurality of pixels; and
a non-display area surrounding the display area;
each of the plurality of pixels comprises a display pixel circuit; and
the non-display area comprises one or more test pixel circuits, each of the one or more test pixel circuits having an equivalent circuit structure to the display pixel circuit, where the one or more test pixel circuits include a plurality of transistors, and electrodes of at least one of the plurality of transistors are respectively conductively coupled to different test pads and at least one of the conductive couplings formed through a via penetrating at least one insulating layer.

2. The display panel of claim 1 , wherein the non-display area further comprises:
a plurality of environmental pixel circuits, each of the plurality of environmental pixel circuits having an equivalent circuit structure to the display pixel circuit, where the plurality of environmental pixel circuits surrounds at least one of the one or more test pixel circuits.

3. The display panel of claim 2 , wherein each of the one or more test pixel circuits is surrounded by eight environmental pixel circuits of the plurality of environmental pixel circuits, such that any one of the one or more test pixel circuits and a corresponding eight surrounding environmental pixel circuits are arranged in a 3×3 array, the one of the one or more test pixel circuits included in the 3×3 array being located at a center of the 3×3 array.

4. The display panel of claim 2 , wherein
the one or more test pixel circuits comprise one or more 3×3 arrays of test pixel circuits; and
each of the one or more 3×3 arrays of test pixel circuits is surrounded by sixteen environmental pixel circuits of the plurality of environmental pixel circuits, such that any one of the one or more 3×3 arrays of test pixel circuits and a corresponding sixteen surrounding environmental pixel circuits are arranged in a 5×5 array, the one of the one or more 3×3 arrays of test pixel circuits included in the 5×5 array being located at a center of the 5×5 array.

5. The display panel of claim 2 , wherein
the non-display area is divided into a test area and a border area adjacent to the test area; and
each of the one or more test pixel circuits and the plurality of environmental pixel circuits are located in the test area and/or the border area.

6. The display panel of claim 1 , wherein electrodes of each of the plurality of transistors included in the one or more test pixel circuits are respectively conductively coupled to different test pads.

7. The display panel of claim 6 , wherein each of the one or more test pixel circuits comprises a first group of transistors, the first group of transistors comprising a driving thin-film transistor (TFT), the driving TFT comprising a gate electrode, a source electrode, and a drain electrode, the gate electrode conductively coupled to a gate test pad, the source electrode conductively coupled to a source test pad, and the drain electrode conductively coupled to a drain test pad.

8. The display panel of claim 6 , wherein
the one or more test pixel circuits include a first group of transistors, each of the first group of transistors comprising a first transistor and a second transistor, the first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, the second transistor comprising a second gate electrode, a second source electrode, and second drain electrode; and
the first gate electrode is conductively coupled to a first gate test pad, the first source electrode is conductively coupled to a first source test pad, the first drain electrode is conductively coupled to a first drain test pad, the second gate electrode is conductively coupled to a second gate test pad, the second source electrode is conductively coupled to a second source test pad, and the second drain electrode is conductively coupled to a second drain test pad.

9. The display panel of claim 8 , wherein the first gate test pad and the second gate test pad are a common gate test pad.

10. The display panel of claim 8 , wherein the first gate test pad and the second gate pad are a common gate test pad, and the first drain test pad and the second drain test pad are a common drain test pad.

11. The display panel of claim 8 , wherein the first gate test pad and the second gate pad are a common gate test pad, and the first source test pad and the second source test pad are a common source test pad.

12. The display panel of claim 1 , wherein the one or more test pixel circuits comprise:
an active layer, a first insulating layer, a first gate electrode layer, a second insulating layer, a second gate electrode layer, a third insulating layer, a source/drain electrode layer, a fourth insulating layer, a test electrode layer, and a fifth insulating layer sequentially stacked on a base substrate;
wherein, for each of the plurality of transistors:
a gate is located in the first gate electrode layer;
a source and a drain are located in the source/drain electrode layer;
the source/drain electrode layer has a gate connection pad and a source/drain connection pad;
the gate connection pad is conductively coupled to the gate through a first via hole penetrating the third insulating layer and the second insulating layer;
the second gate electrode layer has a second via hole for avoiding the gate connection pad;
the source/drain connection pad is conductively coupled to the active layer through third via holes penetrating the third insulating layer, the second insulating layer, and the first insulating layer;
the second gate electrode layer has fourth via holes for avoiding the source/drain connection pad;
the test electrode layer has a gate test pad and a source/drain test pad;
the gate test pad is conductively coupled to the gate connection pad through a fifth via hole penetrating the fourth insulating layer;
the source/drain test pad is conductively coupled to the source/drain connection pad through sixth via holes penetrating the fourth insulating layer; and
the fifth insulating layer has seventh and eighth via holes respectively exposing the gate test pad and the source/drain test pad.

13. The display panel of claim 12 , wherein each of the one or more test pixel circuits comprises:
a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a driving transistor, and a capacitor;
wherein a gate of the driving transistor is conductively coupled to a first electrode of the capacitor and a drain of the first switching transistor;
the drain of the first switching transistor is conductively coupled to a source of the second switching transistor;
a source of the driving transistor is conductively coupled to a drain of the second switching transistor and a source of the fifth switching transistor;
a drain of the driving transistor is conductively coupled to a drain of the third switching transistor and a drain of the fourth switching transistor;
a second electrode of the capacitor is conductively coupled to a source of the fourth switching transistor; and
a drain of the fifth switching transistor is conductively coupled to a drain of the sixth switching transistor.

14. A method for detecting electrical properties of a display panel, the method comprising:
conductively coupling an electrical test device to at least one test pad; and
controlling the electrical test device to perform an electrical test on the elec

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Bao Zheng
• Xia Yaqin
• Xin Yanxia
• Chen Gong
• Hu Hongwei
• Wu Yihao
• Li Xueping

Classifications

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/006

  Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

• G09G2330/12

  Test circuits or failure detection circuits included in a display system, as permanent part thereof · CPC title

• G09G2320/029

  by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title