Semiconductor device with integrated memory devices and MOS devices and process of making the same

US11444095B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11444095-B2
Application numberUS-202117229848-A
CountryUS
Kind codeB2
Filing dateApr 13, 2021
Priority dateDec 22, 2019
Publication dateSep 13, 2022
Grant dateSep 13, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, comprising: a substrate with a first area and a second area; multiple double-diffused metal-oxide-semiconductor (DMOS) devices on said first area, wherein said double-diffused metal-oxide-semiconductor (DMOS) device comprises a field oxide on said substrate, a first gate dielectric layer adjacent to said field oxide, and a first polysilicon gate on said field oxide and said first gate dielectric layer; and multiple memory units on said second area, wherein said memory unit comprises an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on said oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of said second polysilicon gate of said memory unit in said second area and a top surface of said first polysilicon gate of said double-diffused metal-oxide-semiconductor (DMOS) in said first area are on the same level. 2. The semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices of claim 1 , further comprising multiple complementary metal-oxide-semiconductor (CMOS) devices in said first area, wherein said complementary metal-oxide-semiconductor (CMOS) device comprises a second gate dielectric layer and a third polysilicon gate on said second gate dielectric layer, and a top surface of said third polysilicon gate of said complementary metal-oxide-semiconductor (CMOS) is on the same level as said top surface of said first polysilicon gate of said double-diffused metal-oxide-semiconductor (DMOS) in said first area and said top surface of said second polysilicon gate of said memory unit in said second area. 3. The semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices of claim 2 , wherein said first gate dielectric layers of said DMOS device is thicker than said second gate dielectric layers of said CMOS device. 4. The semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices of claim 1 , wherein said first polysilicon gate of said double-diffused metal-oxide-semiconductor (DMOS) partly overlaps said field oxide at one sides. 5. The semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices of claim 1 , wherein said memory unit is silicon-oxide-nitride-oxide-silicon (SONOS) memory.

Assignees

Inventors

Classifications

  • Photolithographic processes · CPC title

  • using masks for insulating materials · CPC title

  • using masks for conductive or resistive materials · CPC title

  • the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

  • the material being a silicon oxide, e.g. SiO2 · CPC title

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What does patent US11444095B2 cover?
A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the…
Who is the assignee on this patent?
United Microelectronics Corp
What technology area does this patent fall under?
Primary CPC classification H01L27/11568. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 13 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).