Method of making memory cells, high voltage devices and logic devices on a substrate

Patent metadata

Field	Value
Publication number	US-11444091-B2
Application number	US-202017129865-A
Country	US
Kind code	B2
Filing date	Dec 21, 2020
Priority date	Jun 23, 2020
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the first and second areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in the first and second areas, forming a protective layer in the first and second areas and then removing the second conductive layer from the third area, then forming blocks of conductive material in the third area, then etching in the first and second areas to form select and HV gates, and replacing the blocks of conductive material with blocks of metal material.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
providing a substrate of semiconductor material that includes a first area, a second area and a third area;
recessing an upper surface of the substrate in the first area and an upper surface of the substrate in the second area relative to an upper surface of the substrate in the third area;
forming a first conductive layer disposed over and insulated from the upper surfaces in the first and second areas;
forming a second conductive layer disposed over and insulated from the first conductive layer in the first and second areas, and disposed over and insulated from the upper surface in the third area;
performing one or more etches to selectively remove portions of the first and second conductive layers in the first area, to entirely remove the first and second conductive layers from the second area, while maintaining the second conductive layer in the third area, wherein the one or more etches result in pairs of stack structures in the first area with each of the stack structures including a control gate of the second conductive layer disposed over and insulated from a floating gate of the first conductive layer;
forming first source regions in the substrate each disposed between one of the pairs of stack structures;
forming a third conductive layer disposed over and insulated from the upper surfaces of the substrate in the first and second areas;
forming a protective layer over the third conductive layer in the first and second areas;
after the forming of the protective layer, removing the second conductive layer from the third area;
after the removing of the second conductive layer from the third area, forming blocks of conductive material disposed over and insulated from the upper surface in the third area;
after the forming of the blocks of conductive material in the third area, etching portions of the protective layer and portions of the third conductive layer in the first and second areas to form a plurality of select gates of the third conductive layer each disposed adjacent to one of the stack structures and to form a plurality of HV gates of the third conductive layer each disposed over and insulated from the upper surface in the second area, wherein for each of the pairs of stack structures, an erase gate of the third conductive layer is disposed between the pair of stack structures, and over and insulated from one of the source regions;
after the forming of the plurality of select gates and the plurality of HV gates:
forming a semi-nonconformal layer of flowable material in the first, second and third areas,
removing a portion of the semi-nonconformal layer of flowable material from the protective layer in the first area while maintaining the semi-nonconformal layer of flowable material in the second and third areas,
thinning the protective layer in the first area, and
removing remaining portions of semi-nonconformal layer of flowable material in the first area and the semi-nonconformal layer of flowable material in the second and third areas;

forming first drain regions in the substrate each adjacent to one of the select gates;
forming second source regions in the substrate each adjacent one of the HV gates;
forming second drain regions in the substrate each adjacent one of the HV gates;
forming third source regions in the substrate each adjacent one of the blocks of conductive material;
forming third drain regions in the substrate each adjacent one of the blocks of conductive material;
removing the thinned protective layer in the first area to expose the select gates and the erase gate;
forming silicide on the select gates and the erase gates; and
replacing each of the blocks of conductive material with a block of metal material.

2. The method of claim 1 , wherein each of the blocks of metal material is insulated from the upper surface in the third area by a layer of high K insulation material.

3. The method of claim 1 , wherein before the replacing, each of the blocks of conductive material is insulated from the upper surface in the third area by a layer of high K insulation material, and wherein the replacing further comprises forming each of the blocks of metal material on the layer of high K insulation material.

4. The method of claim 1 , wherein each of the first, second and third conductive layers is formed of polysilicon or amorphous silicon.

5. The method of claim 1 , wherein the forming of the first conductive layer further includes forming the first conductive layer in the third area, and wherein the method further comprises removing the first conductive layer from the third area.

6. The method of claim 1 , wherein the forming of the third conductive layer further includes forming the third conductive layer in the third area, and wherein the method further comprises removing the third conductive layer from the third area.

7. The method of claim 1 , further comprising:
forming silicide on the first, second and third drain regions and on the second and third source regions.

8. The method of claim 1 , further comprising:
forming silicide on the HV gates.

9. The method of claim 8 , wherein after the forming of the silicide on the select gates, the erase gates and the HV gates, and before the replacing each of the blocks of conductive material with the block of metal material, the method further comprising:
forming a protective layer of material on the silicide in the first and second areas.

10. The method of claim 1 , wherein for each of the stack structures, the control gate is insulated from the floating gate by an ONO insulation layer.

11. The method of claim 1 , wherein after the forming of the third conductive layer, the method further comprising:
forming a layer of insulation material on the third conductive layer in the second area;
forming a dummy layer of conductive material on the third conductive layer in the first and third areas and on the layer of insulation material in the second area;
performing a chemical mechanical polish to remove the dummy layer of conductive material in the first, second and third areas; and then
removing the layer of insulation material from the second area.

Assignees

• Silicon Storage Tech Inc

Inventors

• Sun Jack
• Wang Chunming
• Liu Xian
• Yang Andy
• Song guo xiang
• Xing leo
• Do Nhan

Classifications

• H01L29/66825

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L29/42328

  Electricity · mapped topic

• H01L27/11529

  Electricity · mapped topic

• H01L27/11531 Primary

  Electricity · mapped topic