Mask design for embedded memory

Patent metadata

Field	Value
Publication number	US-10325919-B1
Application number	US-201816015480-A
Country	US
Kind code	B1
Filing date	Jun 22, 2018
Priority date	Jun 22, 2018
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

Various embodiments of the present application are directed to a method for forming an integrated circuit (IC), and the associated integrated circuit. In some embodiments, a stack of gate dielectric precursor layers is formed on a plurality of logic sub-region and is then selectively removed from at least two logic sub-regions. Then, a gate dielectric precursor layer is formed, and a plasma treatment process and an annealing process are subsequently performed. The gate dielectric precursor layer is then selectively removed from a low-voltage logic sub-region, but not a high-voltage logic sub-region. By removing the stack of gate dielectric precursor layers from the low-voltage logic sub-region prior to performing the plasma treatment process and the annealing process, less gate dielectric precursor material is treated, annealed, and removed from the low-voltage logic sub-region. Thus, the resulting residues are reduced, and the defects introduced by the residues are also reduced or eliminated.

First claim

The invention claimed is:

1. A method for forming an integrated circuit (IC), the method comprising:
providing a substrate including a logic region, wherein the logic region has a plurality of logic sub-regions;
forming a stack of gate dielectric precursor layers on the plurality of logic sub-regions;
removing the stack of gate dielectric precursor layers from at least two logic sub-regions of the logic region;
forming a gate dielectric precursor layer on the at least two logic sub-regions of the logic region;
performing a plasma treatment process and an annealing process to the stack of gate dielectric precursor layers and the gate dielectric precursor layer; and
removing the gate dielectric precursor layer from a low-voltage logic sub-region of the at least two logic sub-regions of the logic region without removing the gate dielectric precursor layer from a high-voltage logic sub-region of the at least two logic sub-regions of the logic region, wherein the low-voltage logic sub-region has a logic device configured to operate at a voltage smaller than that of another logic device of the high-voltage logic sub-region.

2. The method according to claim 1 , wherein the stack of gate dielectric precursor layers comprises at least a first gate dielectric precursor layer, a second gate dielectric precursor layer, and a third gate dielectric precursor layer stacked one above another.

3. The method according to claim 1 , further comprising:
forming a low-voltage gate dielectric precursor layer on the substrate at the low-voltage logic sub-region and on the gate dielectric precursor layer at the high-voltage logic sub-region;
patterning the low-voltage gate dielectric precursor layer to form a low-voltage logic gate dielectric overlying the low-voltage logic sub-region; and
patterning the gate dielectric precursor layer and the low voltage gate dielectric precursor layer to collectively form a high-voltage logic gate dielectric overlying the high-voltage logic sub-region.

4. The method according to claim 3 , wherein the low-voltage gate dielectric precursor layer comprises a high κ dielectric liner stacked on a silicon dioxide layer.

5. The method according to claim 3 , further comprising:
forming and patterning a conductive layer overlying the low-voltage logic sub-region and the high-voltage logic sub-region to respectively form a high-voltage logic gate electrode on the high-voltage logic gate dielectric and a low-voltage logic gate electrode on the low-voltage logic gate dielectric.

6. The method according to claim 5 , further comprising:
forming a memory cell structure on a memory region of the substrate, wherein the memory region is separated from the logic region by a boundary region defined therebetween; and
forming a dummy capping layer covering the memory cell structure;
wherein the stack of gate dielectric precursor layers is formed on the dummy capping layer after the forming of the dummy capping layer.

7. The method according to claim 6 , further comprising:
removing the dummy capping layer from the memory region;
forming source/drain regions on opposite sides of the memory cell structure and within the memory region, and further on opposite sides of the high-voltage logic gate electrode and the low-voltage logic gate electrode and within the logic region;
forming a contact etch stop layer (CESL) along an outline of the memory cell structure and the logic devices; and
forming a lower inter-layer dielectric layer between and over the memory cell structure and the logic devices.

8. The method according to claim 5 , further comprising:
replacing the high-voltage logic gate electrode or the low-voltage logic gate electrode with a metal gate electrode.

9. The method according to claim 7 , further comprising:
forming an upper inter-layer dielectric layer over the lower inter-layer dielectric layer; and
forming contacts extending through the upper inter-layer dielectric layer and the lower inter-layer dielectric layer respectively to the source/drain regions in the memory region and the logic region.

10. The method according to claim 6 , wherein forming the memory cell structure comprises:
forming a pair of floating gate electrodes on the substrate;
forming a pair of control gate electrodes respectively on the floating gate electrodes; and
forming a pair of select gate electrodes laterally alongside the floating gate electrodes and the control gate electrodes.

11. A method for forming an integrated circuit (IC), the method comprising:
providing a substrate comprising a logic region and a memory region separated by a boundary region, wherein the logic region comprises a first logic sub-region, a second logic sub-region, a third logic sub-region, a fourth logic sub-region, and a fifth logic sub-region;
forming a first gate dielectric precursor layer on the substrate and covering the first, second, third, fourth, and fifth logic sub-regions;
selectively removing the first gate dielectric precursor layer from the second logic sub-region without removing the first gate dielectric precursor layer from the first, third, fourth, and fifth logic sub-regions;
forming a second gate dielectric precursor layer on the first gate dielectric precursor layer and the substrate, and further covering the first, second, third, fourth, and fifth logic sub-regions;
selectively removing the first and second gate dielectric precursor layers from the third logic sub-region;
forming a third gate dielectric precursor layer on the second gate dielectric precursor layer and the substrate, and further covering the first, second, third, fourth, and fifth logic sub-regions;
selectively removing the first, second, and third gate dielectric precursor layers from the fourth and fifth logic sub-regions;
forming a fourth gate dielectric precursor layer on the third gate dielectric precursor layer and the substrate, and further covering the first, second, third, fourth, and fifth logic sub-regions; and
selectively removing the fourth gate dielectric precursor layer from the fifth logic sub-region.

12. The method according to claim 11 , further comprising:
forming a fifth gate dielectric precursor layer on the fourth gate dielectric precursor layer at the first, second, third, and fourth logic sub-regions, and further on the substrate at the fifth logic sub-region;
forming a logic gate layer on the fifth gate dielectric precursor layer; and
performing an etch to the logic gate layer and the first, second, third, fourth, and fifth gate dielectric precursor layers to form first, second, third, fourth, and fifth logic gate electrodes and first, second, third, fourth, and fifth logic gate dielectrics correspondingly stacked on the first, second, third, fourth, and fifth logic sub-regions.

13. The method according to claim 12 , further comprising:
forming a memory cell structure on the memory region of the substrate; and
forming a dummy capping layer covering the memory cell structure;
wherein the logic gate layer and the first, second, third, fourth, and fifth gate dielectric precursor layers are formed on the dummy capping layer after the forming of the dummy capping layer, and wherein the logic gate layer and the first, second, third, fourth, and fifth gate dielectric precursor layers are removed from the dummy capping layer when performing the etch to form the first, second, third, fourth, and fifth logic gate electrodes and the first, second, third, fourth, and fifth logic gate dielectrics.

14. The method according to claim 12 , wherein the fifth gate dielectric precursor layer comprises a high κ dielectric liner stacked on

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Teng Li-Feng
• Wu Wei Cheng

Classifications

• H01L27/11529

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/11546 Primary

  Electricity · mapped topic

• H10D30/6892 Primary

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/681

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title