Shift register, gate drive circuit, display panel and driving method

Patent metadata

Field	Value
Publication number	US-11443684-B2
Application number	US-202017006755-A
Country	US
Kind code	B2
Filing date	Aug 28, 2020
Priority date	Jun 24, 2020
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

Provided are a shift register, a gate drive circuit, a display panel and a driving method. The shift register includes a first output module, a second output module, a first node, a second node, a first power supply signal terminal, a first clock signal terminal and a scan output terminal. The first output module and the second output module are electrically connected to the scan output terminal. The first output module is further electrically connected to the first power supply signal terminal and the first node. The first node is configured to control a conduction state of the first output module. The second output module is further electrically connected to the first clock signal terminal and the second node. The second node is configured to control a conduction state of the second output module. There is no capacitor in the first output module and/or the second output module.

First claim

What is claimed is:

1. A shift register, comprising: a first output module, a second output module, a first node, a second node, a first power supply signal terminal, a first clock signal terminal and a scan output terminal;
wherein the first output module and the second output module are electrically connected to the scan output terminal;
wherein the first output module is further electrically connected to the first power supply signal terminal and the first node, the first node is configured to control a conduction state of the first output module, and during the first output module conducting, a voltage signal input by the first power supply signal terminal is output to the scan output terminal;
wherein the second output module is electrically connected to the first clock signal terminal and the second node, wherein the second node is configured to control a conduction state of the second output module, and during the second output module conducting, a voltage signal input by the first clock signal terminal is output to the scan output terminal; and
wherein there is no capacitor in at least one of the first output module or the second output module;
wherein the shift register further comprises: a first node control module, a second node control module, a node mutual control module, a first shift input terminal, a first level signal terminal, a second clock signal terminal and a second power supply signal terminal; wherein the first node control module and the second node control module are electrically connected to the first level signal terminal;
wherein the first node control module is further electronically connected to the second clock signal terminal, the second power supply signal terminal and the first node; and the first node control module is configured to control a potential of the first node according to a voltage signal input by the first level signal terminal, a voltage signal input by the second clock signal terminal and a voltage signal input by the second power supply signal terminal,
wherein the second node control module is further electronically connected to the first shift input terminal and the second node; and the second node control module is configured to control a potential of the second node according to a voltage signal input by the first level signal terminal and a voltage signal input by the first shift input terminal; and
wherein the node mutual control module is electronically connected to the first node, the second node and the first power supply signal terminal; and the node mutual control module is configured to control the potential of the second node according to the potential of the first node, or control the potential of the first node according to the potential of the second node.

2. The shift register of claim 1 , wherein the first output module comprises a first transistor, and the second output module comprises a second transistor;
wherein a gate of the first transistor is electrically connected to the first node, a first electrode of the first transistor is electrically connected to the first power supply signal terminal, and a second electrode of the first transistor is electrically connected to the scan output terminal;
wherein a gate of the second transistor is electrically connected to the second node, a first electrode of the second transistor is electrically connected to the first clock signal terminal, and a second electrode of the second transistor is electrically connected to the scan output terminal.

3. The shift register of claim 2 , wherein at least one of a channel's width/length (W/L) ratio of the first transistor or a channel's W/L ratio of the second transistor is greater than 45.

4. The shift register of claim 1 ,
wherein the first node control module comprises a third transistor and a fourth transistor;
wherein a gate of the third transistor is electrically connected to a second electrode of the fourth transistor, a first electrode of the third transistor is electrically connected to the second power supply signal terminal, a second electrode of the third transistor is electrically connected to the first node, a first electrode of the fourth transistor is electrically connected to the second clock signal terminal, and a gate of the fourth transistor is electrically connected to the first level signal terminal;
wherein the second node control module comprises a fifth transistor; wherein a gate of the fifth transistor is electrically connected to the first shift input terminal, a first electrode of the fifth transistor is electrically connected to the first level signal terminal, and a second electrode of the fifth transistor is electrically connected to the second node; and
wherein the node mutual control module comprises a sixth transistor and a seventh transistor; wherein a gate of the sixth transistor is electrically connected to the first node, a first electrode of the sixth transistor is electrically connected to the first power supply signal terminal, a second electrode of the sixth transistor is electrically connected to the second node, a gate of the seventh transistor is electrically connected to the second node, a first electrode of the seventh transistor is electrically connected to the first power supply signal terminal, and a second electrode of the seventh transistor is electrically connected to the first node.

5. The shift register of claim 4 , wherein a channel's W/L ratio of the fifth transistor is at least two times or larger than a channel's W/L ratio of any transistor in the node mutual control module.

6. The shift register of claim 4 , further comprising a tenth transistor; wherein a gate of the tenth transistor is electrically connected to the second power supply signal terminal, a first electrode of the tenth transistor is electrically connected to the second node, and a second electrode of the tenth transistor is electrically connected to the second output module.

7. The shift register of claim 1 , further comprising: a second shift input terminal, a second level signal terminal and a third clock signal terminal;
wherein the second node control module and the first node control module are electrically connected to the second level signal terminal; the second node control module is further electrically connected to the second shift input terminal; and the third clock signal terminal is electrically connected to the first node control module;
wherein the first node control module is configured to control the potential of the first node according to a voltage signal input by the first level signal terminal, a voltage signal input by the second level signal terminal, a voltage signal input by the second clock signal terminal, a voltage signal input by the third clock signal terminal and a voltage signal input by the second power source signal terminal; and
wherein the second node control module is configured to control the potential of the second node according to a voltage signal input by the first level signal terminal, a voltage signal input by the second level signal terminal, a voltage signal input by the first shift input terminal and a voltage signal input by the second shift input terminal.

8. The shift register of claim 7 ,
wherein the first node control module comprises a third transistor, a fourth transistor and an eighth transistor; wherein a second electrode of the fourth transistor and a second electrode of the eighth transistor are electrically connected to a gate of the third transistor;
wherein first electrode of the third transistor is electrically connected to the second power supply signal terminal;
wherein a second electrode of the third transistor is electrically connected to the first node; a first electrode of the fourth transistor is electric

Assignees

• Xiamen Tianma Micro Electronics Co Ltd

Inventors

• Li Donghua
• Wei Xiaoli
• Lai Guochang
• Li Junyi

Classifications

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/2092 Primary

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title