Secure debug architecture

Patent metadata

Field	Value
Publication number	US-11443071-B2
Application number	US-202016790222-A
Country	US
Kind code	B2
Filing date	Feb 13, 2020
Priority date	Feb 13, 2020
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

Systems and methods are disclosed for secure debug architecture. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions; a debug interface comprising two or more conductors with input/output drivers configured to, when enabled, transmit and receive signals between the processor core and an external host device via the two or more conductors; and wherein the integrated circuit is configured to: receive a request from a host device for access to the integrated circuit via the debug interface; responsive to the request, generate a random number; transmit the random number from the integrated circuit to the host device via the debug interface; receive, from the host device via the debug interface, input data that has been encrypted using the random number as a key; and decrypt the input data using the random number as a key.

First claim

What is claimed is:

1. An integrated circuit for executing instructions comprising:
a processor core configured to execute instructions;
a debug interface comprising two or more conductors with input/output drivers configured to, when enabled, transmit and receive signals between the processor core and an external host device via the two or more conductors, wherein the debug interface includes an authorization register that is updated to enable or disable the connection between the debug interface and the processor core;
an authentication circuit comprising an authenticated register; and
wherein the integrated circuit is configured to:
receive a request from a host device for access to the integrated circuit via the debug interface;
responsive to the request, generate a random number;
transmit the random number from the integrated circuit to the host device via the debug interface;
receive, from the host device via the debug interface, input data that has been encrypted using the random number as a key, wherein the input data includes at least one of a debug command and a firmware image;
decrypt the input data using the random number as a key: and
update content of the authenticated register based on comparison of the input data to a value stored in non-volatile memory of the integrated circuit, wherein the authentication circuit is configured to update content of the authorization register based on the content of the authenticated register.

2. The integrated circuit of claim 1 , in which the authentication circuit is configured to:
compare an identifier received via the debug interface to an identifier of the integrated circuit that is stored in non-volatile memory of the integrated circuit; and
responsive to the received identifier matching the identifier of the integrated circuit, updating a register to indicate the match and cause the random number to be generated and transmitted.

3. The integrated circuit of claim 2 , in which the authentication circuit is configured to:
compare a portion of the input data to a value stored in non-volatile memory of the integrated circuit; and
responsive to a match between the portion of the input data and the value, enable the debug interface to provide access to the processor core.

4. The integrated circuit of claim 3 , in which the value is a part number or a serial number of the integrated circuit.

5. The integrated circuit of claim 1 , in which the integrated circuit is configured to:
encrypt output data using the random number as a key; and
transmit the encrypted output data to the host device via the debug interface.

6. The integrated circuit of claim 1 , in which the integrated circuit is configured to:
encrypt the random number to obtain an encrypted random number; and
transmit the encrypted random number to the host device via the debug interface.

7. The integrated circuit of claim 6 , in which the random number is encrypted for transmission using a public key stored in the integrated circuit that corresponds to a private key stored by the host device that can be used to decrypt the encrypted random number.

8. The integrated circuit of claim 1 , in which the input data includes signed data that has been signed using a signing key.

9. The integrated circuit of claim 1 , in which the input data includes debug commands for the processor core.

10. The integrated circuit of claim 1 , in which the input data includes a firmware image.

11. A method comprising:
receiving a request from a host device for access to an integrated circuit via a debug interface of the integrated circuit;
responsive to the request, generating a random number using the integrated circuit;
transmitting the random number from the integrated circuit to the host device via the debug interface;
receiving, from the host device via the debug interface, input data that has been encrypted using the random number as a key, wherein the input data includes at least one of a debug command and a firmware image;
decrypting the input data, within the integrated circuit, using the random number as a key; and
update content of an authenticated register in an authentication circuit based on comparison of the input data to a value stored in non-volatile memory of the integrated circuit, wherein the authentication circuit is configured to update content of an authorization register in the debug interface based on the content of the authenticated register.

12. The method of claim 11 , comprising:
encrypting output data, within the integrated circuit, using the random number as a key; and
transmitting the encrypted output data to the host device via the debug interface.

13. The method of claim 11 , in which the request is received from the host device via a debug probe connecting the host device to the debug interface of the integrated circuit.

14. The method of claim 11 , in which transmitting the random number from the integrated circuit to the host device via the debug interface comprises:
encrypting the random number using the integrated circuit to obtain an encrypted random number; and
transmitting the encrypted random number from the integrated circuit to the host device via the debug interface.

15. The method of claim 14 , in which the random number is encrypted for transmission using a public key stored in the integrated circuit that corresponds to a private key stored by the host device that can be used to decrypt the encrypted random number.

16. The method of claim 11 , in which the input data includes signed data that has been signed using a signing key.

17. The method of claim 16 , comprising:
comparing an identifier in the request to an identifier of the integrated circuit that is stored in non-volatile memory of the integrated circuit; and
responsive to the identifier in the request matching the identifier of the integrated circuit, updating a register to indicate the match and cause the random number to be generated and transmitted.

18. A method comprising:
transmitting a request from a host device for access to an integrated circuit via a debug interface of the integrated circuit;
receiving, using the host device, a random number from the integrated circuit via the debug interface;
encrypting, on the host device, input data using the random number as a key, wherein the input data includes at least one of a debug command and a firmware image;
signing data using a signing key to obtain signed data, in which the input data includes the signed data; and
transmitting from the host device to the integrated circuit via the debug interface the encrypted input data.

19. The method of claim 18 , comprising:
receiving, on the host device, output data from the integrated circuit via the debug interface; and
decrypting, on the host device, the output data using the random number as a key.

20. The method of claim 18 , in which the request is transmitted via a debug probe connecting the host device to the debug interface of the integrated circuit.

21. The method of claim 18 , in which receiving the random number from the integrated circuit via the debug interface comprises:
receiving an encrypted random number from the integrated circuit via the debug interface; and
decrypting the encrypted random number to obtain the random number.

22. The method of claim 21 , in which the encrypted random number is decrypted using a private key stored in the host device that corresponds to a public key stored by the integrated circuit

Assignees

• Sifive Inc

Inventors

• Loisel Yann
• Lhermet Frank

Classifications

• G06F2221/033

  Test or assess software · CPC title

• G06F21/72 Primary

  in cryptographic circuits · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• H04L9/0662

  with particular pseudorandom sequence generator · CPC title

• G06F21/606

  by securing the transmission between two devices or processes · CPC title