Error management in system on a chip with securely partitioned memory space
US-12517841-B2 · Jan 6, 2026 · US
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Loisel Yann patents
Loisel Yann is listed as an inventor on 9 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Loisel Yann |
| Total patents | 9 |
| First publication | Jan 26, 2016 |
| Latest publication | Jan 6, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Debug in system on a chip with securely partitioned memory space
US-12399721-B2 · Aug 26, 2025 · US
Debug In System On A Chip With Securely Partitioned Memory Space
US-2024338221-A1 · Oct 10, 2024 · US
Error Management In System On A Chip With Securely Partitioned Memory Space
US-2024303205-A1 · Sep 12, 2024 · US
Secure control flow prediction
US-2022292183-A1 · Sep 15, 2022 · US
Secure debug architecture
US-11443071-B2 · Sep 13, 2022 · US
Secure debug architecture
US-2021256164-A1 · Aug 19, 2021 · US
Data interleaving scheme for an external memory of a secure microcontroller
US-10797857-B2 · Oct 6, 2020 · US
Keypad having tamper-resistant keys
US-9245702-B1 · Jan 26, 2016 · US
Recent patents
Latest publications not already listed above.
No data yet.
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Sifive Inc | 7 |
| Maxim Integrated Products | 2 |
| Debout Vincent | 1 |
| Lhermet Frank | 1 |
| Loisel Yann | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F21/74 | 4 |
| G06F2212/1052 | 4 |
| G06F12/1491 | 4 |
| G06F12/1441 | 4 |
| G06F11/3648 | 4 |