Multibit vectored sequential with scan

Patent metadata

Field	Value
Publication number	US-11442103-B2
Application number	US-202117240877-A
Country	US
Kind code	B2
Filing date	Apr 26, 2021
Priority date	Dec 18, 2017
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

First claim

We claim:

1. An apparatus comprising:
a first scan control input;
a second scan control input;
a scan input;
a first tri-stateable inverter controllable by a buffered version of the first scan control input and an inverted version of the first scan control input, wherein the first tri-stateable inverter is to receive the scan input;
a second tri-stateable inverter controllable by a buffered version of the second scan control input and an inverted version of the second scan control input, wherein the second tri-stateable inverter is to receive an output of the first tri-stateable inverter;
a memory circuitry coupled to an output of the second tri-stateable inverter;
a third tri-stateable inverter coupled to the memory circuitry and the output of the second tri-stateable inverter, wherein the third tri-stateable inverter is controlled by the buffered version of the first scan control input and the inverted version of the first scan control input.

2. The apparatus of claim 1 comprising a pass-gate controllable by the buffered version of the first scan control input and the inverted version of the first scan control input, wherein the pass-gate is coupled to the output of the first tri-stateable inverter.

3. The apparatus of claim 2 , wherein the pass-gate is part of a memory circuitry of a data path.

4. The apparatus of claim 3 , wherein the memory circuitry of the data path includes:
an inverter coupled to the pass-gate;
a fourth tri-stateable inverter controllable by a clock and an inverse of the clock, wherein an input of the fourth tri-stateable inverter is coupled to the pass-gate, the first tri-stateable inverter, and the second tri-stateable inverter, and wherein an output of the fourth tri-stateable inverter is coupled to an input of the inverter.

5. The apparatus of claim 4 , wherein the inverter is a first inverter, wherein the pass-gate is a first pass-gate, wherein the data path comprises:
a second inverter to receive a data input; and
a second pass-gate coupled to an output of the second inverter, wherein the second pass-gate is coupled to the first inverter and the fourth tri-stateable inverter, wherein the second pass-gate is controllable by the clock and the inverse of the clock.

6. The apparatus of claim 1 comprising:
a fifth tri-stateable inverter controllable by the buffered version of the second scan control input and the inverted version of the second scan control input, wherein the fifth tri-stateable inverter is to receive an output of the third tri-stateable inverter.

7. The apparatus of claim 6 , wherein the memory circuitry is a first memory circuitry, wherein the apparatus comprises:
a second memory circuitry coupled to an output of the fifth tri-stateable inverter.

8. The apparatus of claim 7 comprising a sixth tri-stateable inverter coupled to the second memory circuitry and the output of the fifth tri-stateable inverter, wherein the sixth tri-stateable inverter is controlled by the buffered version of the first scan control input and the inverted version of the first scan control input.

9. An apparatus comprising:
a processor circuitry;
a memory coupled to the processor circuitry;
a communication interface to allow the processor circuitry to communicate with another device, wherein the processor circuitry includes:
a first circuitry including a first sequential circuitry and a second sequential circuitry; and
a second circuitry to provide a scan of data associated with the first circuitry, wherein the second circuitry comprises a first bit-cell and a second bit-cell, wherein a portion of the first bit-cell of the second circuitry is part of a feedback path of the first sequential circuitry, and wherein a portion of the second bit-cell of the second circuitry is part of a feedback path of the second sequential circuitry.

10. The apparatus of claim 9 , wherein an output of the first bit-cell is coupled to an input of the second bit-cell.

11. The apparatus of claim 9 , wherein the first comprises a clock buffer shared by the first and second sequential circuitries.

12. The apparatus of claim 9 , wherein the feedback path of the first sequential circuitry comprises a latch.

13. The apparatus of claim 9 , wherein the second comprises buffers to generate control signals, and wherein the buffers are shared by the first and second bit-cells.

14. The apparatus of claim 9 , wherein the portion of the first bit-cell comprises a pass-gate.

15. An apparatus comprising:
a processor circuitry;
a memory coupled to the processor circuitry;
a communication interface to allow the processor circuitry to communicate with another device, wherein the processor circuitry includes:
a first scan control input;
a second scan control input;
a scan input;
a first tri-stateable inverter controllable by a buffered version of the first scan control input and an inverted version of the first scan control input, wherein the first tri-stateable inverter is to receive the scan input;
a second tri-stateable inverter controllable by a buffered version of the second scan control input and an inverted version of the second scan control input, wherein the second tri-stateable inverter is to receive an output of the first tri-stateable inverter;
a memory circuitry coupled to an output of the second tri-stateable inverter;
a third tri-stateable inverter coupled to the memory circuitry and the output of the second tri-stateable inverter, wherein the third tri-stateable inverter is controlled by the buffered version of the first scan control input and the inverted version of the first scan control input.

16. The apparatus of claim 15 comprising a pass-gate controllable by the buffered version of the first scan control input and the inverted version of the first scan control input, wherein the pass-gate is coupled to the output of the first tri-stateable inverter.

17. The apparatus of claim 16 , wherein the pass-gate is part of a memory circuitry of a data path.

18. The apparatus of claim 17 , wherein the memory circuitry of the data path includes:
an inverter coupled to the pass-gate;
a fourth tri-stateable inverter controllable by a clock and an inverse of the clock, wherein an input of the fourth tri-stateable inverter is coupled to the pass-gate, the first tri-stateable inverter, and the second tri-stateable inverter, and wherein an output of the fourth tri-stateable inverter is coupled to an input of the inverter.

19. The apparatus of claim 18 , wherein the inverter is a first inverter, wherein the pass-gate is a first pass-gate, wherein the data path comprises:
a second inverter to receive a data input; and
a second pass-gate coupled to an output of the second inverter, wherein the second pass-gate is coupled to the first inverter and the fourth tri-stateable inverter, wherein the second pass-gate is controllable by the clock and the inverse of the clock.

20. The apparatus of claim 19 comprising:
a fifth tri-stateable inverter controllable by the buffered version of the second scan control input and the inverted version of the second scan control input, wherein the fifth tri-stateable inverter is to receive an output of the third tri-stateable inverter.

21. The apparatus of claim 20 , wherein the memory circuitry is a first memory circuitry, wherein the apparatus comprises:
a second memory circuitry coupled to an output of the fifth tri-stateable inverter.

22. The apparatus of claim 21 comprising a sixth tri-stateable inverter coupl

Assignees

• Intel Corp

Inventors

• Agarwal Amit
• Krishnamurthy Ram
• Damaraju Satish
• Hsu Steven
• REALOV Simeon

Classifications

• G01R31/31723 Primary

  Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926) · CPC title

• H03K3/0372 Primary

  of the primary-secondary type · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/318541

  Scan latches or cell details · CPC title

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title