Component carrier and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11439018-B2
Application number	US-202017247884-A
Country	US
Kind code	B2
Filing date	Dec 29, 2020
Priority date	Dec 29, 2020
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure. A cavity is formed in the stack and has a non-polygonal outline. A component is in the cavity. A method of manufacturing such a component carrier is also provided.

First claim

The invention claimed is:

1. A component carrier, comprising:
a stack comprising at least one electrically conductive layer structure and/or at least one electrically insulating layer structure;
a cavity formed in the stack, the cavity having a non-polygonal outline; and
a component in the cavity, the component having a linear sidewall adjacent to a nonlinear portion of the cavity.

2. The component carrier according to claim 1 , wherein
the non-polygonal outline includes a discontinuity.

3. The component carrier according to claim 1 , wherein
a rounding in a corner of the non-polygonal outline has a radius of at least 0.05 mm.

4. The component carrier according to claim 1 , wherein
the non-polygonal outline is substantially rectangular with an extension in at least one corner of the non-polygonal outline.

5. The component carrier according to claim 1 , wherein
the non-polygonal outline is nonlinear along its entire perimeter.

6. The component carrier according to claim 1 , wherein
at least a portion of the non-polygonal outline is rounded.

7. The component carrier according to claim 1 , wherein
the component has a polygonal outline.

8. The component carrier according to claim 1 , wherein
the component has a chamfered edge.

9. The component carrier according to claim 1 , wherein
a volume between the component and walls of the stack delimiting the cavity is configured as a stress buffer.

10. The component carrier according to claim 1 , wherein
a volume between the component and walls of the stack delimiting the cavity is at least partially filled with a fiber-free resin.

11. The component carrier according to claim 10 , wherein
the fiber-free resin is inserted into the volume by laminating at least one further at least partially uncured electrically insulating layer structure on the stack and the component in the cavity.

12. The component carrier according to claim 1 , wherein
the at least one electrically insulating layer structure has sidewalls delimiting at least a part of the cavity and comprises fibers.

13. The component carrier according to claim 1 , wherein
the component is a ceramic block or a copper block.

14. The component carrier according to claim 1 , wherein
a difference between an area delimited by the outline and an area of the component is adjusted to be substantially proportional to a square root of the area of the component.

15. The component carrier according to claim 1 , wherein
the component has a stepped profile at at least one of its main surfaces and is laterally engaged by a resin clamping structure.

16. A method of manufacturing a component carrier, the method comprising:
providing a stack comprising at least one electrically conductive layer structure and/or at least one electrically insulating layer structure;
forming in the stack a cavity having a non-polygonal outline; and
inserting a component in the cavity, the component having a linear sidewall adjacent to a nonlinear portion of the cavity.

17. The method according to claim 16 , wherein a difference between an area delimited by the non-polygonal outline and an area of the component is adjusted to be substantially proportional to a square root of the area of the component.

18. The method according to claim 16 , wherein the component has a stepped profile at at least one of its main surfaces and is laterally engaged by a resin clamping structure.

Assignees

• At & S Austria Tech & Systemtechnik Ag

Inventors

• Liebfahrt Sabine
• Lutschounig Ferdinand
• Reitmaier Bernhard
• Platzer Julia
• Frewein Markus

Classifications

• H05K1/0271 Primary

  Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion · CPC title

• H05K1/183 Primary

  associated with components mounted in and supported by recessed areas of the PCBs · CPC title

• H05K1/185

  associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards · CPC title

• H05K2201/09854

  Hole or via having special cross-section, e.g. elliptical · CPC title

• H05K3/4694

  Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density (H05K3/4691 takes precedence) · CPC title