Circuit board and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016374189-A1
Application number	US-201615070294-A
Country	US
Kind code	A1
Filing date	Mar 15, 2016
Priority date	Jun 18, 2015
Publication date	Dec 22, 2016
Grant date	—

Abstract

Disclosed are a circuit board and a method of manufacturing the same. The circuit board includes a core layer comprising a first surface and a second surface opposing the first surface, at least one first build-up layer formed on the first surface, and comprising a first conductive pattern and a first conductive via, at least one second build-up layer formed on the second surface, and comprising a second conductive pattern and a second conductive via, a cavity formed to pass through the core layer, the first build-up layer and the second build-up layer, and a heat dissipation unit disposed inside the cavity, and an outer layer formed on a surface of the first build-up layer and a surface of the second build-up layer and the outer layer being configured to be connected to the heat dissipation unit.

First claim

What is claimed is:

1 . A circuit board comprising:
a core layer comprising a first surface and a second surface opposing the first surface; at least one first build-up layer formed on the first surface, and comprising a first conductive pattern and a first conductive via; at least one second build-up layer formed on the second surface, and comprising a second conductive pattern and a second conductive via; a cavity formed to pass through the core layer, the first build-up layer and the second build-up layer, and a heat dissipation unit disposed inside the cavity; and an outer layer formed on a surface of the first build-up layer and a surface of the second build-up layer and the outer layer being configured to be connected to the heat dissipation unit.

2 . The circuit board of claim 1 , wherein the outer layer fills a space between the heat dissipation unit and an inner wall of the cavity.

3 . The circuit board of claim 1 , wherein a thickness of the heat dissipation unit is greater than that of the core layer.

4 . The circuit board of claim 3 , wherein the thickness of the heat dissipation unit is at least 80% of a depth of the cavity.

5 . The circuit board of claim 1 , wherein a first portion of a surface of the heat dissipation unit near an edge of at least one of the upper surface or the lower surface is covered by the outer layer and a second portion of the surface of the heat dissipation unit is exposed.

6 . The circuit board of claim 1 , wherein at least one of the upper surface or the lower surface of the heat dissipation unit is covered by the outer layer.

7 . The circuit board of claim 1 , wherein at least one of the outer layer comprises opening parts to expose a portion of the upper surface or the lower surface of the heat dissipation unit.

8 . The circuit board of claim 1 , wherein at least one of the first build-up layer and the second build-up layer comprises a plurality of build-up layers, and the cavity passes through the plurality of build-up layers.

9 . The circuit board of claim 1 , wherein at least one of the first build-up layer and the second build-up layer comprises a plurality of build-up layers, and the cavity does not pass through an outermost build-up layers.

10 . The circuit board of claim 1 , wherein a heat dissipation via is formed in the outermost built-up layer, and the heat dissipation via is directly connected to the heat dissipation unit.

11 . The circuit board of claim 1 , wherein the outer layer comprises a solder resist.

12 . The circuit board of claim 1 , wherein the circuit board comprises a chip mounting area, and the cavity has a smaller area than the surface area of chip mounting area, and the cavity is arranged inside the chip mounting area.

13 . The circuit board of claim 1 , further comprising a heat dissipation metal layer formed on at least one of the upper surface or the lower surface of the heat dissipation unit, and a cross-sectional area of the heat dissipation metal layer is greater than a cross-sectional area of the heat dissipation unit.

14 . The circuit board of claim 11 , wherein the heat dissipation unit is spaced apart from an inner wall of the cavity, and the heat dissipation metal layer covers the space formed between the inner wall of the cavity and the heat dissipation unit.

15 . The circuit board of claim 11 , wherein a side surface of the heat dissipation metal layer is connected with the conductive pattern.

16 . The circuit board of claim 11 , wherein the outer layer has opening parts to expose at least a portion of the outermost surface of the heat dissipation metal layer.

17 . A circuit board comprising:
a build-up laminate comprising build-up layers, each layer of the build-up layers comprising a conductive pattern and a conductive via; a cavity formed to pass through the build-up layers; a heat dissipation unit disposed inside the cavity; and an outer layer formed on the surface of the build-up laminate and the outer layer being disposed on at least a portion of the heat dissipation unit.

18 . A method for manufacturing a circuit board comprising:
preparing a core layer comprising a first surface and a second surface opposing the first surface; preparing a board laminate by forming at least one first build-up layer formed on the first surface and at least one second build-up layer formed on the second surface; forming a conductive pattern and a conductive via on each of the first build-up layer and the second build-up layer; forming a cavity to pass through the board laminate; arranging a heat dissipation unit inside the cavity; and forming an outer layer on a surface of the first build-up layer and a surface of the second build-up layer to be connected to the heat dissipation unit.

19 . The method of claim 14 , wherein a width of the heat dissipation unit is smaller than a width of the cavity, and the arranging of the heat dissipation unit comprises arranging the board laminate on a supporting film and arranging the heat dissipation unit inside the cavity at a distance from an inner wall of the cavity.

20 . The method of claim 15 , wherein the forming of the outer layer comprises:
forming a first outer layer on one surface of the first build-up layer to fill the space between the inner wall of the cavity and the heat dissipation unit; and forming a second outer layer on the surface of the second build-up layer after eliminating the supporting film.

21 . The method of claim 16 , further comprising eliminating a portion of the outer layer to expose a part of the conductive pattern formed on the each surface of the first build-up layer, the second build-up layer, and a part of the heat dissipation unit.

Assignees

• Samsung Electro Mech

Inventors

• Lee Jae-Seok

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H05K1/115

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K3/10

  in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• H05K2201/09063

  Holes or slots in insulating substrate not used for electrical connections · CPC title