Three-dimensional memory device with source structure and methods for forming the same

Patent metadata

Field	Value
Publication number	US-11437398-B2
Application number	US-202016863203-A
Country	US
Kind code	B2
Filing date	Apr 30, 2020
Priority date	Mar 2, 2020
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack over a substrate, a plurality of channel structures, a source structure, and a support structure. The memory stack includes interleaved a plurality of conductor layers and a plurality of insulating layers. The plurality of channel structures extend vertically in the memory stack. The source structure includes a plurality of source portions and extending in the memory stack. The support structure is between adjacent ones of the source portions and has a plurality of interleaved conductor portions and insulating portions. A top one of the conductor portions is in contact with a top one of the conductor layers. Adjacent ones of the source portions are conductively connected to one another.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a memory stack over a substrate, the memory stack comprising interleaved a plurality of conductor layers and a plurality of insulating layers;
a plurality of channel structures extending vertically in the memory stack;
a source structure comprising a plurality of source portions and extending in the memory stack; and
a support structure between adjacent ones of the source portions and comprising a plurality of interleaved conductor portions and insulating portions, wherein
a top one of the conductor portions is in contact with and conductively connected to a top one of the conductor layers, and
adjacent ones of the source portions are conductively connected to one another.

2. The 3D memory device of claim 1 , wherein the source structure further comprises a connection layer in contact with and conductively connected to the adjacent ones of the source portions, the connection layer being a conductive layer.

3. The 3D memory device of claim 2 , wherein the connection layer comprises at least one of tungsten, cobalt, aluminum, copper, silicides, or polysilicon.

4. The 3D memory device of claim 2 , wherein the connection layer is positioned over each of the adjacent ones of the source portions.

5. The 3D memory device of claim 4 , wherein the connection layer is over the support structure.

6. The 3D memory device of claim 4 , wherein the support structure is in contact with memory blocks adjacent to the source structure.

7. The 3D memory device of claim 6 , wherein
each of the conductor portions is in contact with conductor layers of a same level in the memory blocks and each of the insulating portions is in contact with insulating layers of the same level in the memory blocks; and
the conductor portions and the conductor layers comprise the same materials, and the insulating portions and the insulating layers comprise the same materials.

8. The 3D memory device of claim 1 , wherein
the top one of the conductor portions of the support structure is higher than top surfaces of the adjacent ones of the source portions.

9. The 3D memory device of claim 2 , further comprising a cap layer over the source structure, wherein:
the cap layer covers a pair of first portions of the connection layer that are over the adjacent ones of the source portions and exposes a second portion of the connection layer that is over the support structure; and
a top surface of the second portion of the connection layer is higher than top surfaces of the pair of first portions of the connection layer.

10. The 3D memory device of claim 2 , wherein the connection layer is over and in contact with each of the plurality of source contacts.

11. A three-dimensional (3D) memory device, comprising:
a memory stack comprising a plurality of memory blocks over a substrate, each of the memory blocks comprising interleaved a plurality of conductor layers and a plurality of insulating layers;
a plurality of channel structures extending vertically in the memory blocks;
a source structure extending between adjacent memory blocks; and
a support structure in contact with the source structure and comprising a plurality of interleaved conductor portions and insulating portions, wherein
adjacent memory blocks are in contact with each other through the support structure, and
a top one of the conductor portions is in direct contact with a top one of the conductor layers in each of the adjacent memory blocks.

12. The 3D memory device of claim 11 , wherein the source structure comprises a plurality of source portions, adjacent ones of the source portions are conductively connected to one another.

13. The 3D memory device of claim 12 , wherein the source structure further comprises a connection layer in contact with and conductively connected to the adjacent ones of the source portions, the connection layer being a conductive layer.

14. The 3D memory device of claim 13 , wherein the connection layer comprises at least one of tungsten, cobalt, aluminum, copper, silicides, or polysilicon.

15. The 3D memory device of claim 14 , wherein the connection layer is positioned over each of the adjacent ones of the source portions and the support structure.

16. The 3D memory device of claim 11 , wherein
each of the conductor portions is in contact with conductor layers of a same level in the adjacent memory blocks and each of the insulating portions is in contact with insulating layers of the same level in the adjacent memory blocks; and
the conductor portions and the conductor layers comprise the same materials, and the insulating portions and the insulating layers comprise the same materials.

17. A three-dimensional (3D) memory device, comprising:
a memory stack over a substrate, the memory stack comprising interleaved a plurality of conductor layers and a plurality of insulating layers;
a plurality of channel structures extending vertically in the memory stack;
a source structure comprising a plurality of source portions and extending in the memory stack; and
a support structure between adjacent ones of the source portions and comprising a plurality of interleaved conductor portions and insulating portions, wherein
a top one of the conductor portions is coplanar with a top one of the conductor layers, and
adjacent ones of the source portions are conductively connected to one another.

18. The 3D memory device of claim 17 , wherein the source structure further comprises a connection layer in contact with and conductively connected to the adjacent ones of the source portions, the connection layer being a conductive layer.

19. The 3D memory device of claim 18 , wherein the connection layer comprises at least one of tungsten, cobalt, aluminum, copper, silicides, or polysilicon.

20. The 3D memory device of claim 18 , wherein:
the connection layer is positioned over each of the adjacent ones of the source portions; and
the connection layer is over the support structure.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Xu Wenxiang
• Xu Wei
• Huang Pan
• Xia Ji

Classifications

• H01L27/1157

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H10B43/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title