Integrated circuit device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11437382-B2
Application number	US-202016916366-A
Country	US
Kind code	B2
Filing date	Jun 30, 2020
Priority date	Nov 11, 2019
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

An integrated circuit device includes a plurality of semiconductor layers stacked on a substrate to overlap each other in a vertical direction and longitudinally extending along a first horizontal direction. The plurality of semiconductor layers may have different thicknesses in the vertical direction.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a substrate;
a plurality of semiconductor layers on the substrate and overlapping each other in a vertical direction to form a stack, and longitudinally extending in a first horizontal direction and a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction, the plurality of semiconductor layers including a first semiconductor layer and a second semiconductor layer that overlap each other in the vertical direction;
a first gate line and a second gate line that each extend in the vertical direction alongside each of the plurality of semiconductor layers, the first and second gate lines being respectively disposed at opposite sides of the stack in the second horizontal direction; and
capacitors that respectively contact one end of each of the plurality of semiconductor layers in the first horizontal direction, wherein:
the plurality of semiconductor layers have different thicknesses in the vertical direction,
the first semiconductor layer has a first thickness in the vertical direction and a first width in the second horizontal direction,
the second semiconductor layer has a second thickness in the vertical direction and a second width in the second horizontal direction, the second thickness being smaller than the first thickness, the second width being greater than the first width, and
cross-sectional areas of the first and second semiconductor layers are both substantially the same, as determined in a plane that is parallel to the vertical and second horizontal directions.

2. The integrated circuit device as claimed in claim 1 , wherein, among the plurality of semiconductor layers, thicknesses in the vertical direction of respective ones of the semiconductor layers are progressively greater with increasing distance from the substrate, and widths in the second horizontal direction of respective ones of the semiconductor layers are progressively smaller with increasing distance from the substrate.

3. The integrated circuit device as claimed in claim 1 , wherein:
the plurality of semiconductor layers includes:
a third semiconductor layer at a lowest level closest to the substrates;
a fourth semiconductor layer above the first semiconductor layer; and
a fifth semiconductor layer at a highest level farthest from the substrate, and

among the third, fourth, and fifth semiconductor layers, the fourth semiconductor layer has a greatest thickness in the vertical direction.

4. The integrated circuit device as claimed in claim 1 , further comprising of intermediate insulating layers respectively interposed between the plurality of semiconductor layers and overlapping the plurality of semiconductor layers in the vertical direction,
wherein thicknesses in the vertical direction of the intermediate insulating layers are all the same.

5. The integrated circuit device as claimed in claim 1 , wherein each of the plurality of semiconductor layers has a sidewall having an inclined surface forming an angle greater than 0 with respect to a plane along a line normal to a main surface of the substrate.

6. The integrated circuit device as claimed in claim 5 , wherein each of the first and second gate lines is inclined to follow the inclined surface.

7. The integrated circuit device as claimed in claim 1 , wherein the capacitors have respectively different thicknesses in the vertical direction.

8. The integrated circuit device as claimed in claim 7 , further comprising intermediate insulating layers respectively interposed between the plurality of semiconductor layers and overlapping the plurality of semiconductor layers in the vertical direction,
wherein the capacitors are respectively interposed between the intermediate insulating layers.

9. The integrated circuit device as claimed in claim 7 , wherein thicknesses in the vertical direction of respective ones of the capacitors are progressively greater with increasing distance from the substrate.

10. An integrated circuit device, comprising:
a substrate;
a memory cell array on the substrate, the memory cell array including a plurality of memory cells arranged in a first horizontal direction and a second horizontal direction, which are perpendicular to each other, and a vertical direction;
a plurality of semiconductor layers included in a plurality of first memory cells among the plurality of memory cells, the plurality of semiconductor layers being disposed to overlap each other in the vertical direction to form a stack and respectively including a pair of source/drain regions spaced apart from each other in the first horizontal direction and a channel region between the pair of source/drain regions;
a first gate line and a second gate line that each extend in the vertical direction alongside each of the plurality of semiconductor layers, the first and second gate lines being respectively disposed at opposite sides of the stack in the second horizontal direction; and
capacitors that are respectively connected to one end of each of the plurality of semiconductor layers in the first horizontal direction, wherein:
the plurality of semiconductor layers have respectively different thicknesses in the vertical direction, and
cross-sectional areas the plurality of semiconductor layers are all the same, as determined in a plane that is parallel to the vertical and second horizontal directions.

11. The integrated circuit device as claimed in claim 10 , wherein, among the plurality of semiconductor layers, thicknesses in the vertical direction of respective ones of the semiconductor layers are progressively greater with increasing distance from the substrate, and the less widths in the second horizontal direction of respective ones of the semiconductor layers are progressively smaller with increasing distance from the substrate.

12. The integrated circuit device as claimed in claim 10 , wherein:
the plurality of semiconductor layers includes:
a first semiconductor layer at a lowest level closest to the substrates;
a second semiconductor layer above the first semiconductor layer; and
a third semiconductor layer at a highest level farthest from the substrate, and

among the first, second, and third semiconductor layers, the second semiconductor layer has a greatest thickness in the vertical direction.

13. The integrated circuit device as claimed in claim 10 , wherein the plurality of memory cells further includes:
a first gate insulating layer interposed between a first sidewall of each of the plurality of semiconductor layers and the first gate line, and
a second gate insulating layer interposed between a second sidewall of each of the plurality of semiconductor layers and the second gate line.

14. The integrated circuit device as claimed in claim 10 , wherein
the capacitors are disposed to overlap each other in the vertical direction and have respectively different thicknesses in the vertical direction.

15. The integrated circuit device as claimed in claim 14 , wherein thicknesses in the vertical direction of respective ones of the capacitors are progressively greater with increasing distance from the substrate.

16. An integrated circuit device, comprising:
a substrate; and
a plurality of memory cells on the substrate and arranged in a first horizontal direction and a second horizontal direction, which are perpendicular to each other, and a vertical direction, wherein:
the plurality of memory cells includes first memory cells arranged in the vertical direction, the first memory cells including:
a plurality of semicondu

Assignees

• Samsung Electronics Co Ltd

Inventors

• SONG Hyunji
• Kim Jaehoon
• Park Kwangho
• Son Yonghoon
• Lee Gyeonghee
• Jung Seungjae

Classifications

• H01L27/10832 Primary

  Electricity · mapped topic

• H01L27/1087

  Electricity · mapped topic

• H10B12/30 Primary

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H10B12/05

  Making the transistor · CPC title

• H10B12/03

  Making the capacitor or connections thereto · CPC title