Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same

Patent metadata

Field	Value
Publication number	US-9831266-B2
Application number	US-201615225492-A
Country	US
Kind code	B2
Filing date	Aug 1, 2016
Priority date	Nov 20, 2015
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. An alternating sequence of support pedestal structures and conductive rail structures extending along a same horizontal direction are provided between the substrate and the alternating stack. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support pedestal structure. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure, and is electrically isolated from an adjacent support pedestal structure by a portion of a memory film. The conductive rail structures can function as source regions of memory device.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of electrically conductive layers and insulating layers located over a substrate;
an array of memory stack structures, each memory stack structure extending through the alternating stack and including a memory film and a semiconductor channel laterally surrounded by the memory film;
support structures located between the alternating stack and the substrate;
a source conductive layer underlying the alternating stack and overlying the substrate and contacting the support structures; and
conductive rail structures laterally extending along a first horizontal direction, contacting a top surface of the source conductive layer, and contacting sidewalls of the semiconductor channels, wherein the three-dimensional memory device comprises at least one feature selected from:
a first feature that each of the conductive rail structures comprises dimpled sidewalls including respective planar vertical sidewalls adjoined by respective concave vertical sidewalls;
a second feature that each semiconductor channel contacts a sidewall of a respective conductive rail structure, and each memory film contacts a sidewall of a respective support structure; and
a third feature that the support structures comprise a support pedestal structures comprising a first semiconductor material having a doping of a first conductivity type and insulating barrier material below the first semiconductor material, and the conductive rail structures comprise a second semiconductor material having a doping of a second conductivity type that is the opposite of the first conductivity type.

2. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises the first feature.

3. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises the second feature.

4. The three-dimensional memory device of claim 1 , wherein top surfaces of the support structures are within a same horizontal plane as top surfaces of the conductive rail structures.

5. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises the third feature.

6. The three-dimensional memory device of claim 1 , further comprising a backside contact via structure contacting a top surface of the source conductive layer.

7. The three-dimensional memory device of claim 6 , further comprising an insulating spacer laterally surrounding the backside contact via structure and contacting the top surface of the source conductive layer.

8. The three-dimensional memory device of claim 7 , wherein the conductive rail structures are laterally spaced from the backside contact via structure by the insulating spacer.

9. The three-dimensional memory device of claim 1 , wherein each of the support structures comprises dimpled sidewalls including respective planar vertical sidewalls adjoined by respective concave vertical sidewalls.

10. The three-dimensional memory device of claim 9 , wherein each of the concave vertical sidewalls of the support structures contacts an outer sidewall of a respective memory film.

11. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a vertical NAND device located over the substrate;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;
the substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level.

12. A three-dimensional memory device comprising:
an alternating stack of electrically conductive layers and insulating layers located over a substrate;
an array of memory stack structures, each memory stack structure extending through the alternating stack and including a memory film and a semiconductor channel laterally surrounded by the memory film;
support structures located between the alternating stack and the substrate;
a source conductive layer underlying the alternating stack and overlying the substrate and contacting the support structures;
conductive rail structures laterally extending along a first horizontal direction, contacting a top surface of the source conductive layer, and contacting sidewalls of the semiconductor channels;
a backside contact via structure contacting a top surface of the source conductive layer; and
an insulating spacer laterally surrounding the backside contact via structure and contacting the top surface of the source conductive layer,
wherein the conductive rail structures are laterally spaced from the backside contact via structure by the insulating spacer.

13. The three-dimensional memory device of claim 12 , wherein each of the conductive rail structures comprises dimpled sidewalls including respective planar vertical sidewalls adjoined by respective concave vertical sidewalls.

14. The three-dimensional memory device of claim 12 , wherein:
each semiconductor channel contacts a sidewall of a respective conductive rail structure; and
each memory film contacts a sidewall of a respective support structure.

15. The three-dimensional memory device of claim 12 , wherein top surfaces of the support structures are within a same horizontal plane as top surfaces of the conductive rail structures.

16. The three-dimensional memory device of claim 12 , wherein:
the support structures comprise a support pedestal structures comprising a first semiconductor material having a doping of a first conductivity type and insulating barrier material below the first semiconductor material; and
the conductive rail structures comprise a second semiconductor material having a doping of a second conductivity type that is the opposite of the first conductivity type.

17. The three-dimensional memory device of claim 12 , wherein each of the support structures comprises dimpled sidewalls including respective planar vertical sidewalls adjoined by respective concave vertical sidewalls.

18. The three-dimensional memory device of claim 17 , wherein each of the concave vertical sidewalls of the support structures contacts an outer sidewall of a respective memory film.

19. The three-dimensional memory device of claim 12 , wherein:
the three-dimensional memory device comprises a vertical NAND device located over the substrate;
the electrically conductive layers comprise, or are electrica

Assignees

• Sandisk Technologies Llc

Inventors

• Kai James
• Alsmeier Johann
• Liu Jin
• Zhang Yanli

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic