Packaged dies with metal outer layers extending from die back sides toward die front sides

US11437276B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11437276-B2
Application numberUS-202016920462-A
CountryUS
Kind codeB2
Filing dateJul 3, 2020
Priority dateJul 5, 2017
Publication dateSep 6, 2022
Grant dateSep 6, 2022

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method of wafer dicing includes singulating dies from a semiconductor wafer. The method further includes depositing a metal layer on back sides of the singulated dies, wherein a portion of the metal layer continues beyond the backs sides of the singulated dies to deposit at least partially on lateral sides of the singulated dies. A packaged die includes a semiconductor die and a metal outer layer deposited on the back side of the semiconductor die and on a portion of the lateral side of the semiconductor die nearest the back side. The packaged die further includes a substrate mounted to the back side of the semiconductor die a die attach material that bonds the substrate to the metal outer layer deposited on the semiconductor die, wherein the metal outer layer and the die attach material surround the back edge of the semiconductor die.

First claim

Opening claim text (preview).

What is claimed is: 1. A packaged die comprising: a semiconductor die having a front side opposite a back side, a plasma-etched lateral side adjacent to the front side and the back side, and a back edge where the back side and the plasma-etched lateral side meet, the semiconductor die comprising: a base semiconductor substrate; build up layers formed over the base semiconductor substrate to define the front side of the semiconductor die; and a radio frequency (RF) device formed in the base semiconductor substrate and in the build-up layers; a metal outer layer deposited on the back side of the semiconductor die and on a portion of the plasma-etched lateral side of the semiconductor die nearest the back side, wherein the metal outer layer extends on the plasma-etched lateral side from the back side toward the front side, while terminating before reaching the front side of the semiconductor die; a substrate; and an electrically-conductive die attach material bonding the semiconductor die to the substrate, the RF power device electrically coupled to the substrate through the electrically-conductive die attach material and through the metal outer layer. 2. The packaged die of claim 1 , wherein the metal outer layer comprises at least one of: gold; silver; copper; or nickel. 3. The packaged die of claim 1 , wherein the electrically-conductive die attach material comprises: a sintered metal; a conductive adhesive; or a solder. 4. The packaged die of claim 1 , wherein the metal outer layer and the electrically-conductive die attach material extend beyond a width of the back side of the semiconductor die so the back edge of the semiconductor die, where the back side and the plasma-etched lateral side of the semiconductor die meet, is encapsulated by the metal outer layer and the electrically-conductive die attach material. 5. The packaged die of claim 1 , wherein the substrate comprises one or more of gold, silver, copper, nickel and an alloy thereof. 6. The packaged die of claim 1 , wherein the substrate comprises a copper flange. 7. The packaged die of claim 1 , wherein the substrate comprises a metal or metal alloy ground layer over a printed circuit board material. 8. A packaged die comprising: a semiconductor die having a front side opposite a back side, four plasma-etched lateral sides adjacent to the front and back sides, and four back edges where the back side and the four plasma-etched lateral sides meet; a metal outer layer deposited on the back side of the semiconductor die and on portions of the four plasma-etched lateral sides of the semiconductor die nearest the back side, wherein the metal outer layer extends on the four plasma-etched lateral sides from the back side toward the front side, while terminating before reaching the front side of the semiconductor die; a substrate; and a die attach material between the substrate and the metal outer layer, wherein the die attach material bonds the semiconductor die to the substrate, and wherein the die attach material also extends over the metal outer layer on the four plasma-etched lateral sides from the back side toward the front side, while terminating before reaching the front side of the semiconductor die; wherein the semiconductor die comprises a singulated piece of an RF power wafer and contains an RF power device, the RF power device electrically coupled to an electrically-grounded region of the substrate through the die attach material and through the metal outer layer deposited on the back side and the four plasma-etched later sides of the semiconductor die. 9. The packaged die of claim 8 , wherein the metal outer layer comprises at least one of: gold; silver; copper; or nickel. 10. The packaged die of claim 8 , wherein the die attach material comprises: a sintered metal; a conductive adhesive; or a solder. 11. The packaged die of claim 10 , wherein the die attach material comprises: sintered silver; or sintered copper. 12. The packaged die of claim 8 , wherein the substrate comprises one or more of gold, silver, copper, nickel and an alloy thereof. 13. The packaged die of claim 8 , wherein the substrate comprises a copper flange. 14. The packaged die of claim 8 , wherein the substrate comprises a metal or metal alloy ground layer over a printed circuit board material. 15. The packaged die of claim 1 , wherein the metal outer layer directly contacts the back side and plasma-etched lateral side of the semiconductor die. 16. The packaged die of claim 1 , wherein the metal outer layer covers between 20% and 80% of the plasma-etched lateral side of the semiconductor die, by surface area. 17. The packaged die of claim 1 , wherein the plasma-etched lateral side of the semiconductor die has a concave profile. 18. The packaged die of claim 8 , wherein the metal outer layer directly contacts the back side and the four plasma-etched lateral sides of the semiconductor die. 19. The packaged die of claim 8 , wherein the metal outer layer covers between 20% and 80% of the four plasma-etched lateral sides of the semiconductor die, by surface area. 20. The packaged die of claim 8 , wherein at least one of the four plasma-etched lateral sides of the semiconductor die has a concave profile.

Assignees

Inventors

Classifications

  • used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate · CPC title

  • used to protect an active side of a device or wafer · CPC title

  • used during dicing or grinding · CPC title

  • using temporarily an auxiliary support · CPC title

  • Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11437276B2 cover?
A method of wafer dicing includes singulating dies from a semiconductor wafer. The method further includes depositing a metal layer on back sides of the singulated dies, wherein a portion of the metal layer continues beyond the backs sides of the singulated dies to deposit at least partially on lateral sides of the singulated dies. A packaged die includes a semiconductor die and a metal outer l…
Who is the assignee on this patent?
Nxp Usa Inc
What technology area does this patent fall under?
Primary CPC classification H10P54/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 06 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).