Repairable GOA drive system, driving method for GOA circuit, and display panel

US11436973B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11436973-B2
Application numberUS-201817413465-A
CountryUS
Kind codeB2
Filing dateDec 13, 2018
Priority dateDec 13, 2018
Publication dateSep 6, 2022
Grant dateSep 6, 2022

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention relates to a repairable GOA drive system, a driving method for a GOA circuit, and a display panel, which are used to improve the yield of display panels in a manufacturing process. The display panel includes a display area and a pixel circuit arranged in the display area, and the repairable GOA drive system includes a GOA circuit, a repair circuit, and a driver IC. The GOA circuit is connected to a driving signal output end of the driver IC; and the repair circuit is arranged between the driver IC and the pixel circuit and configured to replace at least one abnormal GOA unit in the GOA circuit to output a driving signal to the corresponding pixel circuit when the at least one GOA unit is abnormal. The implementation of the present invention can greatly improve repairability of backplane circuits with a GOA and increase the screen yield in mass production.

First claim

Opening claim text (preview).

What is claimed is: 1. A repairable GOA drive system, used for a display panel comprising a display area and a pixel circuit arranged in the display area, wherein the repairable GOA drive system comprises a GOA circuit, a repair circuit, and a driver IC, wherein the GOA circuit is connected to a driving signal output end of the driver IC; and the repair circuit is arranged between the driver IC and the pixel circuit, and configured to replace at least one abnormal GOA unit in the GOA circuit to output a driving signal to a corresponding pixel circuit when the at least one GOA unit is abnormal, wherein GOA units of the GOA circuit are independent of each other, and each of the GOA units is independently driven by the driver IC via an address bus, wherein a j th stage GOA unit of the GOA circuit correspondingly controls a j th stage horizontal scan line of the pixel circuit in the display area, and j is any integer greater than or equal to 1, wherein the repair circuit is arranged between the pixel circuit and a signal output line of each of the GOA units, and when the j th stage GOA unit in the GOA circuit is abnormal, the j th stage GOA unit is disconnected, and the repair circuit is used to replace the disconnected GOA unit for output, and wherein the repair circuit comprises one or more repair lines, and each of the repair lines is arranged between a signal output line of the GOA unit at each stage and a horizontal scan line arranged corresponding to the GOA unit at a corresponding stage. 2. The repairable GOA drive system according to claim 1 , wherein each of the repair lines is provided with a first interface, and each of the horizontal scan lines is provided with a second interface; wherein when the GOA units operate normally, the first interface is disconnected from the second interface; and when the j th stage GOA unit in the GOA circuit is abnormal, the signal output line of the j th stage GOA unit is disconnected from the j th stage horizontal scan line, and the first interface of one of the repair lines is connected to the second interface of the j th stage horizontal scan line. 3. The repairable GOA drive system according to claim 1 , wherein when the GOA units of the GOA circuit operate normally, the driver IC outputs an address signal to the GOA circuit, to drive a GOA unit corresponding to the address signal to output a driving signal to a horizontal scan line corresponding to the GOA unit. 4. The repairable GOA drive system according to claim 2 , wherein when the j th stage GOA unit in the GOA circuit is abnormal, the driver IC outputs a redundant address signal to suppress outputting signal of the j th stage GOA unit, and outputs a driving signal to the repair circuit, to transmit the driving signal to the j th stage horizontal scan line through the repair circuit. 5. The repairable GOA drive system according to claim 1 , wherein the driver IC comprises a repair logic module, and the repair logic module comprises an address generator, a multiplexer, a storage unit, a comparison unit, and a pulse generation unit; an output end of the address generator is respectively connected to a first input end of the multiplexer and a first input end of the comparison unit, a second input end of the multiplexer is connected to a redundant address, and an output end of the multiplexer is connected to the GOA circuit; and a second input end of the comparison unit is connected to the storage unit, an output end of the comparison unit is respectively connected to a third input end of the multiplexer and an input end of the pulse generation unit, and an output end of the pulse generation unit is connected to a repair line correspondingly arranged in the pixel circuit. 6. The repairable GOA drive system according to claim 5 , wherein the repair logic module further comprises a selection circuit; and an input end of the selection circuit is connected to the output end of the comparison unit, and an output end of the selection circuit is connected to the third input end of the multiplexer. 7. The repairable GOA drive system according to claim 5 , wherein the storage unit comprises a first register, the comparison unit comprises a digital comparator arranged corresponding to the first register, and the pulse generation unit comprises a pulse generator arranged corresponding to the digital comparator; and a first input end of the digital comparator is connected to the output end of the address generator, a second input end of the digital comparator is connected to the correspondingly arranged first register, an output end of the digital comparator is respectively connected to the third input end of the multiplexer and an input end of the correspondingly arranged pulse generator, and an output end of the pulse generator is connected to a repair line correspondingly arranged in the pixel circuit. 8. The repairable GOA drive system according to claim 5 , wherein the driver IC further comprises a voltage conversion unit and an output buffer unit; and an input end of the voltage conversion unit is connected to the output end of the pulse generation unit, an output end of the voltage conversion unit is connected to an input end of the output buffer unit, and an output end of the output buffer unit is connected to a repair line correspondingly arranged in the pixel circuit. 9. The repairable GOA drive system according to claim 5 , wherein at least one redundant address is further preset in the driver IC; and the at least one redundant address does not correspond to any GOA unit in the GOA circuit. 10. A driving method for repairing a GOA circuit, comprising: comparing an input address signal with a stored address of an abnormal GOA unit; and when the input address signal is inconsistent with the address of the abnormal GOA unit: allowing the address signal to pass and gating a corresponding GOA unit; or when the input address signal is consistent with the address of the abnormal GOA unit: suppressing the address signal and sending a driving signal to a pixel circuit corresponding to the abnormal GOA unit through a repair line, and recording the address of the abnormal GOA unit, and storing the address of the abnormal GOA unit in a non-volatile memory that operates in conjunction with the driver IC. 11. The driving method for repairing a GOA circuit according to claim 10 , wherein the suppressing the address signal and sending a driving signal to a pixel circuit corresponding to the abnormal GOA unit through a repair line specifically comprises: inputting a redundant address signal to suppress the address signal; and outputting a driving signal to a repair line, and sending the driving signal to the pixel circuit corresponding to the abnormal GOA unit through the repair line. 12. The driving method for repairing a GOA circuit according to claim 11 , wherein the inputting a redundant address signal and suppressing the address signal by using the redundant address signal; and outputting a driving signal to a repair line, and sending the driving signal to the pixel circuit corresponding to the abnormal GOA unit through the repair line specifically comprises: disconnecting a signal output line of the abnormal GOA unit from a horizontal scan line arranged corresponding to the abnormal GOA unit; and adjusting a connection status between any one of unoccupied repair lines and the horizontal scan line arranged corresponding to the abnormal GOA unit from a disconnected state to a connected state, and marking the selected repair line as being occupied. 13. The driving method for repairing a GOA circuit according to claim 12 , wherein the rep

Assignees

Inventors

Classifications

  • Details of a shift registers arranged for use in a driving circuit · CPC title

  • Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

  • G09G3/32Primary

    semiconductive, e.g. using light-emitting diodes [LED] · CPC title

  • using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

  • Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared · CPC title

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What does patent US11436973B2 cover?
The present invention relates to a repairable GOA drive system, a driving method for a GOA circuit, and a display panel, which are used to improve the yield of display panels in a manufacturing process. The display panel includes a display area and a pixel circuit arranged in the display area, and the repairable GOA drive system includes a GOA circuit, a repair circuit, and a driver IC. The GOA…
Who is the assignee on this patent?
Shenzhen Royole Technologies Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/32. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 06 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).