GOA circuit and driving method thereof, GOA driving circuit, and display device

Patent metadata

Field	Value
Publication number	US-11211022-B2
Application number	US-201716060677-A
Country	US
Kind code	B2
Filing date	Oct 25, 2017
Priority date	Mar 30, 2017
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

The present application provides a GOA circuit, a GOA circuit driving method, a GOA driving circuit and a display device, the GOA circuit includes: a front-end GOA circuit, which is connected to a connection signal input terminal, a reset signal terminal, a first power supply voltage terminal, and a second power supply voltage terminal, a third power supply voltage terminal, a clock signal terminal, and a front-end output terminal, and is configured to output a clock signal at the clock signal terminal to the front-end output terminal when an input signal at the signal input terminal is at an active input level; and a repair circuit, which is connected to the front-end output terminal, a frame start signal, the first power supply voltage terminal, and an output terminal of the GOA circuit.

First claim

What is claimed is:

1. A GOA circuit, comprising:
a front-end GOA circuit which is connected to a signal input terminal, a reset signal terminal, a first power supply voltage terminal, a second power supply voltage terminal, a third power supply voltage terminal, a clock signal terminal, and a front-end output terminal, and is configured to output a clock signal at the clock signal terminal to the front-end output terminal when an input signal at the signal input terminal is at an active input level; and
a repair circuit which is connected to the front-end output terminal, a frame start signal, the first power supply voltage terminal, and an output terminal of the GOA circuit, and is configured to output a pulse at the front-end output terminal to the output terminal of the GOA circuit when the frame start signal is at an active input level; and to make the output terminal of the GOA circuit having no output so that the GOA circuit is in a non-output state when the frame start signal is at an inactive input level,
wherein the repair circuit comprises:
a first repair control transistor having a gate and a first electrode respectively connected to the frame start signal, and a second electrode connected to a reset node;
a second repair control transistor having a gate connected to the reset node, a first electrode connected to the front-end output terminal, and a second electrode connected to the output terminal of the GOA circuit
a first capacitor having a first terminal connected to the reset node; and
a third repair control transistor having a gate connected to an output terminal of a GOA circuit at a next stage, a first electrode connected to a second terminal of the first capacitor, and a second electrode connected to the first power supply voltage terminal.

2. The GOA circuit according to claim 1 , wherein the front-end GOA circuit comprises:
an input circuit, which is connected to the signal input terminal and a pull-up node, and is configured to transfer the input signal to the pull-up node when the input signal of the signal input terminal is at an active input level;
a reset circuit which is connected to the reset signal terminal, the first power supply voltage terminal, and the pull-up node, and is configured to pull down a pull-up signal at the pull-up node to a power supply voltage at the first power supply voltage terminal when a reset signal at the reset signal terminal is at an active control level;
a pull-down control circuit which is connected to the second power supply voltage terminal, the third power supply voltage terminal, the pull-up node, a pull-down node, and the first power supply voltage terminal, and is configured to control whether a pull-down circuit operates;
the pull-down circuit which is connected to the pull-down node, the pull-up node, the first power supply voltage terminal, and the front-end output terminal, and is configured to pull down voltages of the front-end output terminal and the pull-up node to the power supply voltage of the first power supply voltage terminal when a pull-down signal at the pull-down node is at an active pull-down level; and
an output circuit, which is connected to the clock signal terminal, the pull-up node, and the front-end output terminal, and is configured to output the clock signal of the clock signal terminal to the front-end output terminal when the pull-up signal at the pull-up node is at an active pull-up level.

3. The GOA circuit according to claim 2 , wherein the input circuit comprises:
an input transistor having a gate and a first electrode respectively connected to the signal input terminal, and a second electrode connected to the pull-up node.

4. The GOA circuit according to claim 2 , wherein the reset circuit comprises:
a reset transistor having a gate connected to the reset signal terminal, a first electrode connected to the pull-up node, and a second electrode connected to the first power supply voltage terminal.

5. The GOA circuit according to claim 2 , wherein the pull-down control circuit comprises a first pull-down control circuit and a second pull-down control circuit, wherein the pull-down node includes a first pull-down node and a second pull-down node.

6. The GOA circuit according to claim 5 , wherein the first pull-down control circuit comprises:
a first pull-down control transistor having a gate connected to a first pull-down control node, a first electrode connected to the second power supply voltage terminal, and a second electrode connected to the first pull-down node;
a second pull-down control transistor having a gate connected to the pull-up node, a first electrode connected to the first pull-down node, and a second electrode connected to the first power supply voltage terminal;
a third pull-down control transistor having a gate and a first electrode respectively connected to the second power supply voltage terminal, and a second electrode connected to the first pull-down control node; and
a fourth pull-down control transistor having a gate connected to the pull-up node, a first electrode connected to the first pull-down control node, and a second electrode connected to the first power supply voltage terminal, and
the second pull-down control circuit includes:
a fifth pull-down control transistor having a gate connected to a second pull-down control node, a first electrode connected to the third power supply voltage terminal, and a second electrode connected to the second pull-down node;
a sixth pull-down control transistor having a gate connected to the pull-up node, a first electrode connected to the second pull-down node, and a second electrode connected to the first power supply voltage terminal;
a seventh pull-down control transistor having a gate and a first electrode respectively connected to the third power supply voltage terminal, and a second electrode connected to the second pull-down control node; and
an eighth pull-down control transistor having a gate connected to the pull-up node, a first electrode connected to the second pull-down control node, and a second electrode connected to the first power supply voltage terminal.

7. The GOA circuit according to claim 5 , wherein the pull-down circuit includes a first pull down circuit and a second pull-down circuit.

8. The GOA circuit according to claim 7 , wherein the first pull-down circuit comprises:
a first node pull-down transistor having a gate connected to the first pull-down node, a first electrode connected to the pull-up node, and a second electrode connected to the first power supply voltage terminal; and
a first output pull-down transistor having a gate connected to the first pull-down node, a first electrode connected to the front-end output terminal, and a second electrode connected to the first power supply voltage terminal, and
the second pull-down circuit includes:
a second node pull-down transistor having a gate connected to the second pull-down node, a first electrode connected to the pull-up node, and a second electrode connected to the first power supply voltage terminal; and
a second output pull-down transistor having a gate connected to the second pull-down node, a first electrode connected to the front-end output terminal, and a second electrode connected to the first power supply voltage terminal.

9. The GOA circuit according to claim 2 , wherein the output circuit comprises:
an output transistor having a gate connected to the pull-up node, a first electrode connected to the clock signal terminal, and a second electrode connected to the front-end output terminal; and
a second capacitor having a first terminal connected to the pull-up node and a second terminal connected to the front-end output terminal.

10.

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Xiong Xin
• Xiong Xiong
• Liang Hengzhen
• Liu rongcheng

Classifications

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2330/08

  Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G3/3611 Primary

  Control of matrices with row and column drivers · CPC title