DC offset compensation in zero-intermediate frequency mode of a receiver

Patent metadata

Field	Value
Publication number	US-11431359-B2
Application number	US-202017107327-A
Country	US
Kind code	B2
Filing date	Nov 30, 2020
Priority date	Nov 30, 2020
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

A method for operating a radio frequency communications system includes, while operating a first radio frequency communications device in a calibration mode, for each setting of a plurality of settings of a programmable gain amplifier in a receiver of the first radio frequency communications device configured in a zero-intermediate frequency mode of operation, generating an estimate of a DC offset in each of a plurality of digital samples received from an analog circuit path including the programmable gain amplifier, and storing in a corresponding storage element, a compensation value based on the estimate.

First claim

What is claimed is:

1. A method for operating a radio frequency communications system, the method comprising:
while operating a first radio frequency communications device in a calibration mode,
for each setting of a plurality of settings of a programmable gain amplifier in a receiver of the first radio frequency communications device operating in a zero-intermediate frequency mode of operation, generating an estimate of an offset in each of a plurality of digital samples received from a circuit path including the programmable gain amplifier and storing in a corresponding storage element, a compensation value based on the estimate of the offset.

2. The method as recited in claim 1 , wherein in the calibration mode, an input of the receiver is coupled to a reference node to null a receiver input signal.

3. The method as recited in claim 1 , wherein generating the estimate of the offset comprises:
converting in-phase signals generated by the programmable gain amplifier to digital in-phase samples of the plurality of digital samples;
converting quadrature signals generated by the programmable gain amplifier to digital quadrature samples of the plurality of digital samples;
computing a first low-pass filtered signal based on the digital in-phase samples; and
computing a second low-pass filtered signal based on the digital quadrature samples,
wherein the compensation value comprises an in-phase compensation value based on the first low-pass filtered signal and a quadrature compensation value based on the second low-pass filtered signal.

4. The method as recited in claim 3 , wherein the storing occurs after a predetermined number of the digital in-phase samples and the digital quadrature samples are used to compute the first low-pass filtered signal and the second low-pass filtered signal.

5. The method as recited in claim 3 further comprising:
while operating the first radio frequency communications device in the calibration mode:
compensating a digital in-phase sample of the digital in-phase samples with the first low-pass filtered signal to generate a compensated in-phase sample; and
compensating a digital quadrature sample of the digital quadrature samples with the second low-pass filtered signal to generate a compensated quadrature sample,

wherein the storing occurs in response to the compensated in-phase sample or the compensated quadrature sample being below a predetermined threshold value.

6. The method as recited in claim 3 ,
wherein computing the first low-pass filtered signal comprises:
multiplying each first digital in-phase sample received during a first interval by a first coefficient; and
multiplying each second digital in-phase sample received during a second interval by a second coefficient,

wherein computing the second low-pass filtered signal comprises:
multiplying each first digital quadrature sample received during the first interval by the first coefficient; and
multiplying each second digital quadrature sample received during the second interval by the second coefficient, and

wherein a first magnitude of the first coefficient is greater than a second magnitude of the second coefficient and the first interval occurs prior to the second interval.

7. The method as recited in claim 1 further comprising:
while operating the first radio frequency communications device in a zero-intermediate frequency mode of a normal mode of operation of the first radio frequency communications device:
generating offset compensated samples using the compensation value corresponding to an active setting of the plurality of settings of the programmable gain amplifier.

8. The method as recited in claim 7 , wherein in the normal mode of operation, an input of the receiver is communicatively coupled to a radio frequency signal source.

9. The method as recited in claim 7 further comprising:
configuring the programmable gain amplifier to have a first setting of the plurality of settings; and
loading an in-phase compensation value and a quadrature compensation value corresponding to the first setting into a first register of the receiver and a second register of the receiver, respectively,
wherein generating the offset compensated samples includes compensating digital in-phase samples and digital quadrature samples using contents of the first register and the second register, respectively.

10. The method as recited in claim 7 further comprising:
while operating the first radio frequency communications device in the zero-intermediate frequency mode of the normal mode of operation, generating a phase measurement based on the offset compensated samples,
wherein the phase measurement is indicative of a phase difference between a first local oscillator of the first radio frequency communications device and a second local oscillator of a second radio frequency communications device and a distance between the first radio frequency communications device and the second radio frequency communications device.

11. The method as recited in claim 1 , wherein the offset is a direct current (DC) offset.

12. A radio frequency communications system comprising:
a first radio frequency communications device having a calibration mode of operation and a normal mode of operation, the first radio frequency communications device comprising:
a receiver having a zero-intermediate frequency mode of operation and a low-intermediate frequency mode of operation, the receiver comprising:
a circuit path comprising a programmable gain amplifier configurable to have an active setting of a plurality of settings; and
a digital circuit path configured to receive a plurality of digital samples from the circuit path,
wherein, in the calibration mode of operation, the receiver is configured in a zero-intermediate frequency mode and the digital circuit path is configured to generate an estimate of an offset in each of the plurality of digital samples and to store in a storage element corresponding to the active setting, a compensation value based on the estimate of the offset.

13. The radio frequency communications system as recited in claim 12 , wherein in the calibration mode of operation, an input of the receiver is coupled to a reference node to null a receiver input signal.

14. The radio frequency communications system as recited in claim 12 , wherein the digital circuit path comprises:
a first low-pass filter circuit configured to compute a first low-pass filter output based on digital in-phase samples of the plurality of digital samples;
a second low-pass filter circuit configured to compute a second low-pass filter output based on digital quadrature samples of the plurality of digital samples;
a first storage element corresponding to each of the plurality of settings of the programmable gain amplifier;
a second storage element corresponding to each of the plurality of settings of the programmable gain amplifier; and
a control circuit configured to selectively enable each of the plurality of settings as the active setting and to store the first low-pass filter output in the first storage element and to store the second low-pass filter output in the second storage element.

15. The radio frequency communications system as recited in claim 14 ,
wherein the first low-pass filter circuit comprises a multiplier configured to multiply each first digital in-phase sample of the digital in-phase samples received during a first interval by a first coefficient and to multiply each second digital in-phase sample of the digital in-phase samples received during a second interval by a second coefficient, and
wherein the

Assignees

• Silicon Lab Inc

Inventors

• Wu Michael A
• Li Wentao
• Reid Mitchell
• Khoury John M
• Zhou Yan

Classifications

• H04B2001/045

  with means for improving efficiency · CPC title

• H03D3/008

  Compensating DC offsets · CPC title

• H04B1/30

  for homodyne or synchrodyne receivers (demodulator circuits H03D1/22) · CPC title

• H04L25/061

  providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset (removal of DC offset in coupling arrangements H04L25/029, H04L25/0296) · CPC title

• H04B1/04 Primary

  Circuits · CPC title