Self aligned gate connected plates for group III-Nitride devices and methods of fabrication

Patent metadata

Field	Value
Publication number	US-11430873-B2
Application number	US-201816147707-A
Country	US
Kind code	B2
Filing date	Sep 29, 2018
Priority date	Sep 29, 2018
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

A device includes a first Group III-Nitride (III-N) material, a gate electrode above the III-N material, and the gate electrode. The device further includes a tiered field plate, suitable for increasing gate breakdown voltage with minimal parasitics. In the tiered structure, a first plate is on the gate electrode, the first plate having a second sidewall laterally beyond a sidewall of the gate, and above the III-N material by a first distance. A second plate on the first plate has a third sidewall laterally beyond the second sidewall and above the III-N material by a second distance, greater than the first. A source structure and a drain structure are on opposite sides of the gate electrode, where the source and drain structures each include a second III-N material.

First claim

What is claimed is:

1. A device comprising:
a first Group III-Nitride (III-N) material;
a gate electrode above the first III-N material, the gate electrode comprising a first sidewall;
a first plate on the gate electrode, the first plate comprising a second sidewall laterally beyond the first sidewall and above the III-N material by a first distance;
a second plate on the first plate, the second plate comprising a third sidewall laterally beyond the second sidewall and above the III-N material by a second distance, greater than the first distance; and
a source structure and a drain structure on opposite sides of the gate electrode, the source and drain structures each comprising a second III-N material.

2. The device of claim 1 , wherein the gate electrode, the first plate, and the second plate comprise a same material.

3. The device of claim 1 , wherein the second sidewall extends beyond the first sidewall by between 5 nm and 200 nm.

4. The device of claim 1 , wherein the third sidewall extends beyond the second sidewall by between 5 nm and 500 nm.

5. The device of claim 1 , wherein the first plate has a thickness between 10 nm and 100 nm, the second plate has a thickness between 10 nm and 100 nm, and the gate electrode has a thickness between 10 nm and 100 nm.

6. The device of claim 1 , wherein the third sidewall is over at least one of the source structure or the drain structure.

7. The device of claim 1 , wherein the gate electrode has a first width within a cross-sectional plane that intersects the source and drain, the first plate has a second width within the cross-sectional plane, and the second plate has a third width within the cross sectional plane, wherein the third width is greater than the second width and the second width is greater than the first width, and wherein the gate electrode, the first plate, and the second plate are symmetrical about a center of the first width.

8. The device of claim 7 , further comprising:
a dielectric liner adjacent the first plate, the dielectric liner having a thickness; and wherein a sum of the first width plus two times the sum of the thickness of the dielectric liner is equal to the second width.

9. The device of claim 1 , wherein the gate electrode has a first width within a cross-sectional plane that intersects the source and drain, the first plate has a second width within the cross-sectional plane, and the second plate has a third width within the cross sectional plane, wherein the third width is greater than the second width and the second width is greater than the first width, wherein the gate electrode and the first plate are symmetrically arranged within the cross-sectional plane, and wherein the second plate and the first plate are asymmetrically arranged about a center of the first width.

10. The device of claim 1 , wherein the gate electrode comprises a fourth sidewall opposite the first sidewall, the first plate comprises a fifth sidewall opposite the second sidewall, and the second plate comprises a sixth sidewall opposite the third sidewall, wherein both the fifth sidewall and the sixth sidewall are laterally beyond the fourth sidewall by an equal amount.

11. The device of claim 1 , wherein the device further comprises a gate dielectric layer between the gate electrode and the first III-N material.

12. The device of claim 11 , wherein the gate dielectric layer is adjacent to and in contact with each of the first sidewall, the second sidewall, and the third sidewall.

13. A system comprising:
a processor; and
a radio transceiver coupled to the processor, wherein the transceiver comprises a transistor comprising:
a first Group III-Nitride (III-N) material;
a gate electrode above the first III-N material, the gate electrode comprising a first sidewall;
a first plate on the gate electrode, the first plate comprising a second sidewall laterally beyond the first sidewall and above the III-N material by a first distance;
a second plate on the first plate, the second plate comprising a third sidewall laterally beyond the second sidewall and above the III-N material by a second distance, greater than the first distance; and
a source structure and a drain structure on opposite sides of the gate electrode, the source and drain structures each comprising a second III-N material.

14. The system of claim 13 , wherein the gate electrode has a first width within a cross-sectional plane that intersects the source and drain, the first field plate has a second width within the cross-sectional plane, and the second field plate has a third width within the cross sectional plane, wherein the third width is greater than the second width and the second width is greater than the first width, and wherein the gate electrode, the first field plate, and the second field plate are symmetrical about a center of the first width.

15. The system of claim 14 , wherein the transistor further comprises:
a dielectric liner adjacent the first plate, the dielectric liner having a thickness; and wherein a sum of the first width plus two times the sum of the thickness of the dielectric liner is equal to the second width.

16. The system of claim 13 , wherein the gate electrode, the first plate, and the second plate comprise a same material.

17. The system of claim 13 , wherein the second sidewall extends beyond the first sidewall by between 5 nm and 200 nm, the third sidewall extends beyond the second sidewall by between 5 nm and 500 nm, or the first plate has a thickness between 10 nm and 100 nm, the second plate has a thickness between 10 nm and 100 nm, and the gate electrode has a thickness between 10 nm and 100 nm.

18. The system of claim 13 , wherein the gate electrode comprises a fourth sidewall opposite the first sidewall, the first plate comprises a fifth sidewall opposite the second sidewall, and the second plate comprises a sixth sidewall opposite the third sidewall, wherein both the fifth sidewall and the sixth sidewall are laterally beyond the fourth sidewall by an equal amount.

19. The system of claim 13 , wherein the transistor further comprises a gate dielectric layer between the gate electrode and the first III-N material.

20. The system of claim 13 , wherein the gate dielectric layer is adjacent to and in contact with each of the first sidewall, the second sidewall, and the third sidewall.

Assignees

• Intel Corp

Inventors

• Hafez Walid
• Then Han Wui
• Dasgupta Sansaptak
• Radosavljevic Marko
• Fischer Paul

Classifications

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title