Display panel having power bus line with reduced voltage drop

Patent metadata

Field	Value
Publication number	US-11430858-B2
Application number	US-201916294306-A
Country	US
Kind code	B2
Filing date	Mar 6, 2019
Priority date	Aug 17, 2018
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

A display panel includes a substrate including a first non-display area surrounding a transmission area, a display area on an outer portion of the first non-display area, and a second non-display area surrounding the display area, driving thin film transistors and display elements in the display area, a first power supply line in the second non-display area and extending in a first direction, first driving voltage lines and second driving voltage lines extending in a second direction intersecting with the first direction and spaced apart from each other with the transmission area therebetween, and a power bus line connected to the second driving voltage lines in the first non-display area or second non-display area, the power bus line extending in the first direction. A length of the power bus line in the first direction is less than a length of the first power supply line in the first direction.

First claim

What is claimed is:

1. A display panel, comprising:
a substrate including a first non-display area surrounding a transmission area, a display area on an outer portion of the first non-display area, and a second non-display area surrounding the display area;
driving thin film transistors and display elements in the display area;
a first power supply line in the second non-display area, the first power supply line extending in a first direction;
a plurality of first driving voltage lines and a plurality of second driving voltage lines extending in a second direction intersecting with the first direction and spaced apart from each other with the transmission area therebetween; and
a power bus line connected to the plurality of second driving voltage lines in the first non-display area or the second non-display area, the power bus line extending in the first direction,
wherein a length of the power bus line in the first direction is less than a length of the first power supply line in the first direction.

2. The display panel as claimed in claim 1 , wherein the power bus line is in the second non-display area and is integrated with the plurality of second driving voltage lines.

3. The display panel as claimed in claim 1 , further comprising at least one third driving voltage line extending from the first power supply line in the second direction and connected to the power bus line,
wherein the at least one third driving voltage line, the first power supply line, and the power bus line are integrated with one another.

4. The display panel as claimed in claim 1 , further comprising at least one fourth driving voltage line extending from the first power supply line in the second direction,
wherein an end of the at least one fourth driving voltage line is spaced apart from the power bus line.

5. The display panel as claimed in claim 1 , further comprising a plurality of electrode voltage lines arranged at a different layer from the plurality of first driving voltage lines and the plurality of second driving voltage lines, the plurality of electrode voltage lines extending in the first direction, and intersecting the plurality of first driving voltage lines and the plurality of second driving voltage lines,
wherein the plurality of electrode voltage lines are connected to the plurality of first driving voltage lines and the plurality of second driving voltage lines via a contact hole.

6. The display panel as claimed in claim 5 , wherein a specific resistance of the power bus line is less than a specific resistance of the plurality of electrode voltage lines.

7. The display panel as claimed in claim 5 , wherein at least some of the plurality of electrode voltage lines are connected to one another in a ring shape around the transmission area.

8. The display panel as claimed in claim 5 , wherein each of the driving thin film transistors includes a semiconductor layer and a driving gate electrode, and
the plurality of electrode voltage lines overlap the driving gate electrode to form a storage capacitor.

9. The display panel as claimed in claim 1 , wherein a width of the transmission area in the first direction is greater than a width of the transmission area in the second direction.

10. The display panel as claimed in claim 1 , wherein the power bus line is in the first non-display area at a different layer from the plurality of second driving voltage lines and is connected to the plurality of second driving voltage lines via a contact hole.

11. The display panel as claimed in claim 10 , further comprising a plurality of scan lines extending in the first direction and arched around a boundary of the transmission area,
wherein the power bus line overlaps arched parts in the plurality of scan lines.

12. The display panel as claimed in claim 1 , further comprising an additional power bus line connected to the plurality of first driving voltage lines and extending in the first direction,
wherein the additional power bus line is arranged in the first non-display area.

13. The display panel as claimed in claim 1 , wherein:
the transmission area includes a plurality of transmission areas, and
the first non-display area surrounds the plurality of transmission areas.

14. A display panel comprising:
a substrate including a first non-display area surrounding a transmission area, a display area on an outer portion of the first non-display area, and a second non-display area surrounding the display area;
driving thin film transistors and display elements in the display area;
a first power supply line in the second non-display area, the first power supply line extending in a first direction;
a plurality of first driving voltage lines and a plurality of second driving voltage lines extending in a second direction intersecting the first direction and spaced apart from each other with the transmission area therebetween;
a power bus line connected to the plurality of second driving voltage lines, the power bus line being in the first non-display area or the second non-display area to extend in the first direction; and
a plurality of electrode voltage lines intersecting the plurality of first driving voltage lines and the plurality of second driving voltage lines at a different layer from the plurality of first driving voltage lines and the plurality of second driving voltage lines, the plurality of electrode voltage lines being connected to the plurality of first driving voltage lines and the plurality of second driving voltage lines via a contact hole.

15. The display panel as claimed in claim 14 , wherein a specific resistance of the power bus line is less than a specific resistance of the plurality of electrode voltage lines.

16. The display panel as claimed in claim 14 , wherein at least some of the plurality of electrode voltage lines are connected to one another in a ring shape around the transmission area.

17. The display panel as claimed in claim 14 , wherein each of the driving thin film transistors includes a semiconductor layer and a driving gate electrode, and
the plurality of electrode voltage lines overlap the driving gate electrode to form a storage capacitor.

18. The display panel as claimed in claim 14 , wherein the power bus line is in the second non-display area and is integrated with the plurality of second driving voltage lines.

19. The display panel as claimed in claim 14 , wherein the power bus line is in the first non-display area and is located at a different layer from the plurality of second driving voltage lines to be connected to the plurality of second driving voltage lines via a contact hole.

20. The display panel as claimed in claim 14 , further comprising an additional power bus line connected to the plurality of first driving voltage lines and extending in the first direction, wherein the additional power bus line is in the first non-display area.

Assignees

• Samsung Display Co Ltd

Inventors

• Song Hwayoung
• KA Jihyun
• Eom Kimyeong
• Lee Kwangsae

Classifications

• G09G2310/0251

  Precharge or discharge of pixel before applying new pixel voltage · CPC title

• G09G2310/0262

  The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• H01L27/3279 Primary

  Electricity · mapped topic

• H01L27/3265

  Electricity · mapped topic