Closing block family based on soft and hard closure criteria

Patent metadata

Field	Value
Publication number	US-11429504-B2
Application number	US-202016947712-A
Country	US
Kind code	B2
Filing date	Aug 13, 2020
Priority date	Aug 13, 2020
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

A system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to perform operations, including initializing a block family associated with the memory device and initializing a timer associated with the block family. Responsive to beginning to program a block residing on the memory device, the processing device associates the block with the block family. In response to the timer reaching a soft closure value, the processing device performs a soft closure of the block family; continues to program data to the block; and performs a hard closure of the block family in response to one of the timer reaching a hard closure value or the block family satisfying a hard closure criteria.

First claim

What is claimed is:

1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, the processing device to perform operations, comprising:
initializing a block family associated with the memory device;
initializing a timer associated with the block family;
responsive to beginning to program a block residing on the memory device, associating the block with the block family; and
in response to the timer reaching a soft closure value:
performing a soft closure of the block family;
continuing to program data to the block; and
performing a hard closure of the block family in response to a first of the timer reaching a hard closure value or the block family satisfying a hard closure criteria, wherein satisfying the hard closure criteria comprises determining that there is not sufficient time to fill the block completely with data before the timer reaches the hard closure value.

2. The system of claim 1 , wherein the operations further comprise setting the hard closure value of the timer based on at least one of a workload of the processing device, a reference temperature associated with the block family, or a performance expectation of the processing device.

3. The system of claim 1 , wherein the operations further comprise setting the hard closure value of the timer as the soft closure value plus an additional threshold percentage of the soft closure value.

4. The system of claim 1 , wherein the operations further comprise evaluating the hard closure criteria by:
determining an amount of time until filling the block completely with the data being received from a host system; and
deciding whether to finish programming the block based on the amount of time and a remainder of time left until the timer reaches the hard closure value.

5. The system of claim 4 , wherein the operations further comprise, in response to deciding to not finish programming the block, one of:
leaving empty an unwritten portion of the block; or
writing dummy data to the unwritten portion of the block.

6. The system of claim 4 , wherein the operations further comprise, in response to deciding to not finish programming the block:
creating a first partition of a written portion of the block;
associating the first partition with the block family; and
creating a second partition of an unwritten portion of the block for association with a new block family.

7. The system of claim 4 , wherein, in response to deciding to finish programming the block, the operations further comprise finish programming the block with the data received from the host system before performing the hard closure of the block family.

8. The system of claim 1 , wherein the operations further comprise:
detecting a bit error rate of a previously closed block family that employed the hard closure value, wherein the bit error rate is above a threshold acceptable bit error rate; and
reducing the hard closure value by an amount of time calculated to reduce the bit error rate to below the threshold acceptable bit error rate.

9. The system of claim 1 , wherein the operations further comprise:
detecting a write amplification of a previously closed block family that employed the hard closure value, wherein the write amplification is above a threshold acceptable write amplification; and
increasing the hard closure value by an amount of time calculated to reduce the write amplification to below the threshold acceptable write amplification.

10. A method comprising:
initializing, by a processing device, a block family associated with a memory device;
initializing, by the processing device, a timer associated with the block family;
responsive to beginning to program a block residing on the memory device, associating the block with the block family; and
in response to the timer reaching a soft closure value, the processing device:
performing a soft closure of the block family;
continuing to program data to the block; and
performing a hard closure of the block family in response to a first of the timer reaching a hard closure value or the block family satisfying a hard closure criteria, wherein satisfying the hard closure criteria comprises determining that there is not sufficient time to fill the block completely with data before the timer reaches the hard closure value.

11. The method of claim 10 , further comprising determining the hard closure criteria by:
determining an amount of time until filling the block completely with the data being received from a host system; and
deciding whether to finish programming the block based on the amount of time and a remainder of time left until the timer reaches the hard closure value.

12. The method of claim 11 , further comprising, in response to deciding to not finish programming the block, one of:
leaving empty an unwritten portion of the block; or
writing dummy data to the unwritten portion of the block.

13. The method of claim 11 , further comprising, in response to deciding to not finish programming the block:
creating a first partition of a written portion of the block;
associating the first partition with the block family; and
creating a second partition of an unwritten portion of the block for association with a new block family.

14. The method of claim 11 , wherein, in response to deciding to finish programming the block, the method further comprising to finish programming the block with the data received from the host system before performing the hard closure of the block family.

15. The method of claim 10 , further comprising setting the hard closure value of the timer based on at least one of a workload of the processing device, a reference temperature associated with the block family, or a performance expectation of the processing device.

16. The method of claim 10 , further comprising setting the hard closure value of the timer as the soft closure value plus an additional threshold percentage of the soft closure value.

17. The method of claim 10 , further comprising:
detecting a bit error rate of a previously closed block family that employed the hard closure value, wherein the bit error rate is above a threshold acceptable bit error rate; and
reducing the hard closure value by an amount of time calculated to reduce the bit error rate to below the threshold acceptable bit error rate.

18. The method of claim 10 , further comprising:
detecting a write amplification of a previously closed block family that employed the hard closure value, wherein the write amplification is above a threshold acceptable write amplification; and
increasing the hard closure value by an amount of time calculated to reduce the write amplification to below the threshold acceptable write amplification.

Assignees

• Micron Technology Inc

Inventors

• Sheperek Michael
• Koudele Larry J
• Williams Steven S

Classifications

• G06F11/3058

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• G06F11/3037 Primary

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F11/0757

  by exceeding a time limit, i.e. time-out, e.g. watchdogs · CPC title

• G06F11/1004

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title