Hardware processors and methods for extended microcode patching and reloading

Patent metadata

Field	Value
Publication number	US-11429385-B2
Application number	US-201816236434-A
Country	US
Kind code	B2
Filing date	Dec 29, 2018
Priority date	Dec 29, 2018
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

Hardware processors and methods for extended microcode patching through on-die and off-die secure storage are described. In one embodiment, the additional storage resources used for storing micro-operations are section(s) of a cache that are unused at runtime and/or unused by a configuration of a processor. For example, the additional storage resources may be a section of a cache that is used to store context information from a core when the core is transitioned to a power state that shuts off voltage to the core. Non-limiting examples of such sections are one or more sections for: storage of context information for a transition of a thread to idle or off, storage of context information for a transition of a core for a multiple core processor to idle or off, or storage of coherency information for a transition of a cache coherency circuit (e.g., cache box (CBo)) to idle or off.

First claim

What is claimed is:

1. A processor comprising:
a core comprising:
a fetch circuit to fetch a first instruction, a second instruction, and a third instruction,
a decoder circuit coupled to the fetch circuit to decode the first instruction into a first set of at least one micro-operation, and
an execution circuit to execute micro-operations;

a cache having a section to store context information from the core when the core is transitioned to a power state that shuts off voltage to the core; and
a microcode sequencer of the core coupled to the fetch circuit and comprising a patch memory and a read-only memory that stores a plurality of micro-operations, wherein the microcode sequencer:
sends, to the execution circuit, a second set of at least one micro-operation from the plurality of micro-operations stored in the read-only memory for the second instruction received from the fetch circuit,
causes a store of a third set of at least one micro-operation into a system memory coupled to the processor in response to a microcode patch binary image sent by a manufacturer for the third instruction,
sends, to the execution circuit, a fourth set of at least one micro-operation that, when executed, causes the third set of at least one micro-operation to be loaded into the section of the cache from the system memory, and
causes, in response to the third instruction received from the fetch circuit, the third set of at least one micro-operation to be loaded into the patch memory from the section of the cache, and sends, to the execution circuit, the third set of at least one micro-operation from the patch memory,
wherein, when the third set of at least one micro-operation loaded into the patch memory overwrites at least one of a plurality of micro-operations stored in the patch memory, the microcode sequencer reloads the at least one of the plurality of micro-operations that was overwritten when execution of the third set of at least one micro-operation is complete.

2. The processor of claim 1 , wherein the power state is a C6 power state according to an Advanced Configuration and Power Interface (ACPI) standard.

3. The processor of claim 1 , wherein the read-only memory comprises a fifth set of at least one micro-operation for the third instruction that, when the microcode sequencer causes the fifth set to be executed, causes the third set of at least one micro-operation to be loaded into the patch memory from the section of the cache.

4. The processor of claim 1 , wherein firmware, stored in non-transitory storage coupled to the processor, comprises an instruction that when decoded and executed by the processor causes the processor to insert the third set of at least one micro-operation into the system memory for the third instruction.

5. The processor of claim 1 , wherein the microcode sequencer causes, for a fourth instruction fetched by the fetch circuit, a fifth set of at least one micro-operation, different than the third set, to be loaded into the patch memory from the section of the cache, and sends, to the execution circuit, the fifth set of at least one micro-operation from the patch memory.

6. The processor of claim 1 , wherein the microcode sequencer causes the fourth set of at least one micro-operation to be executed when the core is transitioned to a power state that turns on the voltage to the core.

7. The processor of claim 1 , wherein the microcode sequencer further causes a store of the fourth set of at least one micro-operation into the section of the cache.

8. The processor of claim 1 , wherein the microcode sequencer encrypts the third set of at least one micro-operation into an encrypted third set, and the store of the third set into the system memory is a store of the encrypted third set into the system memory.

9. The processor of claim 8 , wherein execution of the fourth set of at least one micro-operation authenticates and decrypts the encrypted third set into an authenticated and decrypted third set, and the third set that is loaded into the section of the cache from the system memory is the authenticated and decrypted third set.

10. A method comprising:
fetching a first instruction, a second instruction, and a third instruction with a fetch circuit of a core of a processor;
decoding the first instruction into a first set of at least one micro-operation with a decoder circuit of the core;
sending the first set of at least one micro-operation from the decoder circuit to an execution circuit of the core;
storing a third set of at least one micro-operation into a system memory coupled to the processor in response to a microcode patch binary image sent by a manufacturer for the third instruction;
executing a fourth set of at least one micro-operation that causes the third set of at least one micro-operation to be loaded from the system memory into a section of a cache that stores context information from the core when the core is transitioned to a power state that shuts off voltage to the core;
sending, by a microcode sequencer of the core, a second set of at least one micro-operation stored in a read-only memory of the microcode sequencer for the second instruction to the execution circuit of the core;
loading, by the microcode sequencer of the core in response to the third instruction received from the fetch circuit, the third set of at least one micro-operation into a patch memory of the microcode sequencer from the section of the cache;
sending, by the microcode sequencer of the core, the third set of at least one micro-operation from the patch memory to the execution circuit; and
executing the first set, the second set, and the third set of at least one micro-operation with the execution circuit of the core,
wherein, at least when the loading of the third set of at least one micro-operation into the patch memory overwrites at least one of a plurality of micro-operations stored in the patch memory, the method further comprises reloading, by the microcode sequencer, the at least one of the plurality of micro-operations that was overwritten when execution of the third set of at least one micro-operation is complete.

11. The method of claim 10 , wherein the power state is a C6 power state according to an Advanced Configuration and Power Interface (ACPI) standard.

12. The method of claim 10 , wherein, in response to receipt of a request for the third instruction, the microcode sequencer causes execution of a fifth set of at least one micro-operation from the read-only memory that causes the loading of the third set of at least one micro-operation into the patch memory of the microcode sequencer from the section of the cache, and the sending of the third set of at least one micro-operation from the patch memory to the execution circuit.

13. The method of claim 10 , further comprising storing firmware including an instruction in non-transitory storage coupled to the processor, wherein decoding and executing of the instruction from the firmware by the processor causes the storing of the third set of at least one micro-operation for the third instruction into the system memory.

14. The method of claim 10 , further comprising:
storing a fifth set of at least one micro-operation for a fourth instruction in the section of the cache that stores context information from the core when the core is transitioned to the power state that shuts off voltage to the core;
fetching the fourth instruction by the fetch circuit;
loading, by the microcode sequencer of the core, the fifth set of at least one micro-operation into the patch memory of the microcode sequencer from the section of the cache;
sending, by the microcode sequence

Assignees

• Intel Corp

Inventors

• Ghetie Sergiu D

Classifications

• G06F9/268 Primary

  Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs · CPC title

• G06F9/24 Primary

  Loading of the microprogram · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title