Digital linear regulator clamping method and apparatus

Patent metadata

Field	Value
Publication number	US-11429172-B2
Application number	US-202016735563-A
Country	US
Kind code	B2
Filing date	Jan 6, 2020
Priority date	Jan 6, 2020
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

First claim

What is claimed is:

1. An apparatus comprising:
a first voltage regulator (VR) with a first efficiency, an output of the first VR coupled to an input power supply rail via an impedance;
a second VR with a second efficiency, wherein the second efficiency is lower than the first efficiency;
a plurality of power gates coupled in parallel between an output of the second VR and the input power supply rail to clamp a supply voltage on the input power supply rail, wherein individual power gates of the plurality of power gates have a source terminal coupled to the output of the second VR, a drain terminal coupled to the input power supply rail, and a gate terminal always coupled to ground, and wherein the power gates are to turn on when the supply voltage on the input power supply rail falls below a respective threshold voltage of the power gates; and
a load coupled to the input power supply rail.

2. The apparatus of claim 1 , wherein the load is a processor core.

3. The apparatus of claim 1 , wherein the plurality of power gates are located on a same die as the load.

4. The apparatus of claim 1 , wherein the first and second VRs are off-die with respect to the load, and wherein the first and second VRs are located on a motherboard.

5. The apparatus of claim 1 , wherein the power gates have different clamping weights.

6. The apparatus of claim 5 , wherein the power gates are binary weighted.

7. The apparatus of claim 5 , wherein the power gates are thermometer weighted.

8. The apparatus of claim 1 , wherein the second VR is a digital linear voltage regulator (D-LVR).

9. An apparatus comprising:
a first voltage regulator (VR) with a first efficiency, an output of the first VR coupled to an input power supply rail via an impedance;
a second VR with a second efficiency, wherein the second efficiency is lower than the first efficiency;
a plurality of power gates coupled in parallel between an output of the second VR and the input power supply rail to clamp a supply voltage on the input power supply rail, wherein individual power gates of the plurality of power gates have a source terminal coupled to the output of the second VR, a drain terminal coupled to the input power supply rail, and a gate terminal always coupled to ground, and wherein the power gates are to turn on when the supply voltage on the input power supply rail falls below a respective threshold voltage of the power gates; and
a third VR having an input coupled to the input power supply rail; and
a load coupled to an output of the third VR.

10. The apparatus of claim 9 , wherein the load is a processor core.

11. The apparatus of claim 9 , wherein the plurality of power gates are located on a same die as the load.

12. The apparatus of claim 9 , wherein the first and second VRs are off-die with respect to the load.

13. A system comprising:
a motherboard;
a first voltage regulator (VR) on the motherboard, the first VR with a first efficiency and having an output coupled to an input power supply rail via an impedance;
a second VR on the motherboard, the second VR with a second efficiency, wherein the second efficiency is lower than the first efficiency;
a system-on-chip (SOC) on the motherboard, the SOC comprising:
a plurality of power gates coupled in parallel between an output of the second VR and the input power supply rail to clamp a supply voltage on the input power supply rail, wherein individual power gates of the plurality of power gates have a source terminal coupled to the output of the second VR, a drain terminal coupled to the input power supply rail, and a gate terminal always coupled to ground, and wherein the power gates are to turn on when the supply voltage on the input power supply rail falls below a respective threshold voltage of the power gates; and
a processor core coupled to the input power supply rail; and
an antenna coupled to the SOC.

14. The system of claim 13 , wherein an output voltage, on the output of the first VR, is dynamically increased or decreased based on an activity of a third VR.

15. The system of claim 13 , wherein a voltage identification (VID) of the first VR is dynamically adjusted based on an activity of a third VR.

16. The system of claim 13 , wherein the second VR is positioned in a die, and wherein the second VR is in parallel with the first VR with an active load-line.

Assignees

• Intel Corp

Inventors

• Uan-Zo-Li Alexander
• Gorbatov Eugene
• Krishnamurthy Harish
• Lyakhov Alexander
• Leung Patrick
• Gunther Stephen
• Gihon Arik
• Ahmed Khondker
• Lehwalder Philip
• Shekhar Sameer
• Pandit Vishram
• Angel Nimrod
• Zelikson Michael

Classifications

• G05F1/56

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• G06F1/32 Primary

  Means for saving power · CPC title

• G05F1/561 Primary

  Voltage to current converters (amplifiers H03F) · CPC title

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title