Dual voltage high speed receiver with toggle mode

Patent metadata

Field	Value
Publication number	US-11424716-B2
Application number	US-202117185120-A
Country	US
Kind code	B2
Filing date	Feb 25, 2021
Priority date	Dec 21, 2020
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

Storage devices are capable of utilizing receiver devices with native devices configured to support lower voltage supplies for higher read performances. The receiver device may include a current source circuit, first and second stage circuits, and a duty cycle balancer circuit. The first stage circuit may utilize first and second native devices with a threshold voltage (VTH) that enables proper lower voltage operations in saturation at high speeds. The current source stage circuit may utilize a third native device to track a transconductance and provide a reference current that becomes proportional to VTH to maintain tighter gain across process, variation, and temperature (PVT). The second stage circuit may utilize a current folding stage to provide a high gain for faster conversion of intermediate signals. The duty cycle balancer may utilize a fourth native device to balance a rise and fall delay skew across the PVT to maintain tighter duty cycle.

First claim

What is claimed is:

1. An amplifier, comprising:
a first stage circuit configured to:
receive an input signal;
compare a reference signal with the input signal; and
generate a first output signal based on the compared input and reference signals;

a second stage circuit configured to:
receive the first output signal;
convert the first output signal with a current folding stage;
generate a second output signal in response to the converted first output signal; and
a duty cycle balancer circuit configured to provide a duty cycle correction to an output signal generated in response to the second output signal; and

a current source stage circuit configured to track a transconductance based on the output signal and the input signal.

2. The amplifier of claim 1 , wherein:
the first stage circuit includes a first native threshold voltage (NVT) device and a second NVT device,
the first NVT device receives the reference signal, and
the first stage circuit is configured to utilize both first and second NVT devices to enable a toggle mode (TM) between a first supply voltage and a second supply voltage.

3. The amplifier of claim 2 , wherein the first supply voltage is a 1.8 supply voltage, and wherein the second supply voltage is a 1.2 supply voltage.

4. The amplifier of claim 1 , wherein:
the first stage circuit includes a first native threshold voltage (NVT) device and a second NVT device,
the duty cycle balancer circuit includes a third NVT device,
the current source stage circuit includes a fourth NVT device, and
the fourth NVT device of the current source stage circuit is configured to generate a reference current that becomes proportional to a threshold voltage (VTH) of the first NVT device.

5. The amplifier of claim 4 , wherein each of the first, second, third, and fourth NVT devices includes a native NMOS transistor.

6. The amplifier of claim 5 , wherein the respective VTH of each of the first, second, third, and fourth NVT devices is approximately a zero voltage.

7. The amplifier of claim 6 , wherein the first output signal generated from the first stage circuit has a low gain.

8. The amplifier of claim 7 , wherein the second output signal generated from the second stage circuit has a high gain.

9. The amplifier of claim 8 , wherein the second gain of the second stage circuit is substantially greater than the low gain of the first stage circuit.

10. A method for generating dual voltage TM links, comprising:
receiving an input signal at a first NVT device of a first stage circuit;
comparing the input signal with a reference signal at a second NVT device of the first stage circuit, wherein the first and second NVT devices are configured to enable a TM between a first supply voltage and a second supply voltage;
generating a first output signal in response to the compared input and reference signals;
receiving the first output signal at a second stage circuit;
generating a second output signal in response to the first output signal converted through a current folding stage of the second stage circuit;
generating a duty cycle correction to an output signal generated from a duty cycle balancer circuit, wherein the duty cycle correction is configured based on the second output signal, and wherein the duty cycle balancer circuit includes a third NVT device;
tracking a transconductance with a current source stage circuit based on the output and input signals, wherein the current source stage circuit includes a fourth NVT device, and
wherein the fourth NVT device of the current source stage circuit is configured to generate a reference current that becomes proportional to the VTH of the first NVT device.

11. The method of claim 10 , wherein the first supply voltage is a 1.8 supply voltage, and wherein the second supply voltage is a 1.2 supply voltage.

12. The method of claim 11 , wherein each of the first, second, third, and fourth NVT devices includes a native NMOS transistor, and wherein the VTH of each of the first, second, third, and fourth NVT devices is approximately a zero voltage.

13. The method of claim 10 , wherein the first output signal generated from the first stage circuit has a low gain, wherein the second output signal generated from the second stage circuit has a high gain, and wherein the second gain of the second stage circuit is substantially greater than the low gain of the first stage circuit.

14. An amplifier, comprising:
a first stage circuit configured to:
receive an input signal at a first NVT device;
compare the input signal with a reference signal at a second NVT device; and
generate a first output signal based on the compared input and reference signals, wherein the first and second NVT devices are configured to enable a TM between a first supply voltage and a second supply voltage;

a second stage circuit configured to:
receive the first output signal;
convert the first output signal with a current folding stage; and
generate a second output signal in response to the converted first output signal;

a duty cycle balancer circuit configured to provide a duty cycle correction to an output signal generated in response to the second output signal, and wherein the duty cycle balancer circuit includes a third NVT device; and
a current source stage circuit configured to track a transconductance based on the output signal and the input signal, wherein the current source stage circuit includes a fourth NVT device, wherein the fourth NVT device of the current source stage circuit is configured to generate a reference current that becomes proportional to the VTH of the first NVT device, and wherein the VTH of each of the first, second, third, and fourth NVT devices is approximately a zero voltage.

Assignees

• Western Digital Tech Inc

Inventors

• Mathur Shiv
• Savadia Ashish
• K Tejaswini

Classifications

• H03F2200/513

  the amplifier being made for low supply voltages · CPC title

• H03F3/45183 Primary

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• H03F3/45269

  Complementary non-cross coupled types · CPC title

• H03F3/3023

  with asymmetrical driving of the end stage · CPC title

• H03F1/0205 Primary

  in transistor amplifiers · CPC title