Semiconductor element, method for manufacturing same, semiconductor substrate, and crystal laminate structure
US-2017213918-A1 · Jul 27, 2017 · US
Semiconductor device and method of manufacturing the same
US11424322B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11424322-B2 |
| Application number | US-202016784907-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 7, 2020 |
| Priority date | Feb 27, 2019 |
| Publication date | Aug 23, 2022 |
| Grant date | Aug 23, 2022 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A semiconductor device may include: a gallium oxide substrate including a first side surface constituted of a (100) plane, a second side surface constituted of a plane other than the (100) plane, and an upper surface; and an electrode in contact with the upper surface, in which the gallium oxide substrate may include: a diode interface constituted of a pn interface or a Schottky interface; and an n-type drift region connected to the electrode via the diode interface, and a shortest distance between the first side surface and the diode interface is shorter than a shortest distance between the second side surface and the diode interface.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a gallium oxide substrate comprising a first side surface constituted of a (100) plane, a second side surface constituted of a plane other than the (100) plane, and an upper surface; and an electrode in contact with the upper surface, wherein the gallium oxide substrate comprises: a diode interface constituted of a pn interface or a Schottky interface; and an n-type drift region connected to the electrode via the diode interface, and a shortest distance between the first side surface and the diode interface is shorter than a shortest distance between the second side surface and the diode interface. 2. The semiconductor device of claim 1 , wherein the gallium oxide substrate comprises a p-type anode region in contact with the electrode and the drift region, and the diode interface is an interface between the anode region and the drift region. 3. The semiconductor device of claim 1 , wherein the drift region is in Schottky contact with the electrode, and the diode interface is an interface between the electrode and the drift region. 4. The semiconductor device of claim 1 , wherein a length of the first side surface is longer than a length of the second side surface in plan view of the upper surface of the gallium oxide substrate. 5. The semiconductor device of claim 2 , wherein the diode interface extends so as to surround the electrode at the upper surface.
Assignees
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Classifications
Singulating wafers or substrates into multiple chips, i.e. dicing · CPC title
Cutting or separating of wafers, substrates or parts of devices · CPC title
Mechanical treatments, e.g. by ultrasounds · CPC title
Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title
- H10D8/60Primary
Schottky-barrier diodes · CPC title
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- What does patent US11424322B2 cover?
- A semiconductor device may include: a gallium oxide substrate including a first side surface constituted of a (100) plane, a second side surface constituted of a plane other than the (100) plane, and an upper surface; and an electrode in contact with the upper surface, in which the gallium oxide substrate may include: a diode interface constituted of a pn interface or a Schottky interface; and …
- Who is the assignee on this patent?
- Nagaoka Tatsuji, Nishinaka Hiroyuki, Yoshimoto Masahiro, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H10D8/60. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 23 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).