Semiconductor structure and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11423951-B2
Application number	US-202016740482-A
Country	US
Kind code	B2
Filing date	Jan 12, 2020
Priority date	Jan 12, 2020
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

A semiconductor structure and a method of fabricating the same are disclosed. The semiconductor structure comprises an active region over a substrate defining a top surface and a gate structure embedded in the active region. In a cross section of the active region, the gate structure includes a conductive feature having a first width buried in the active region and reaching a first depth therein; an insulating cap having a second width arranged above the conductive feature in the active region and reaching a second depth therein; and a dielectric liner arranged between the active region and the conductive feature. The first width is smaller than the second width.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
an active region formed over a substrate having a stripe planar profile, the active region comprising a top surface; and
a control line structure intercepting the active region at an oblique angle, the control line structure comprising:
a conductive line having a first width crossing through a lower portion of the active region and reaching a first depth under the top surface of the active region;
an insulating cap having a second width arranged above the conductive line and reaching a second depth under the top surface of the active region; and
a dielectric liner interposing between the control line structure and the active region;

wherein the first-width is smaller than the second width.

2. The structure of claim 1 , wherein: the oblique angle between the active region and the control line structure ranges from 65 to about 75 degrees.

3. The structure of claim 1 , wherein: a ratio of the second depth to the first depth ranges from about 0.25 to about 0.67.

4. The structure of claim 1 , wherein: a ratio of the second depth to the first depth ranges from about 0.5 to about 0.9.

5. The structure of claim 1 , wherein: the insulating cap defines a shoulder portion proximate the conductive line, the conductive line is arranged below the shoulder portion of the insulating cap.

6. The structure of claim 5 , wherein: the shoulder portion of the insulating cap includes a sloped profile with width reducing toward the conductive line.

7. The structure of claim 1 , wherein: the dielectric liner extends upward between the insulating cap and the active region.

8. The structure of claim 7 , wherein: the portion of the dielectric liner between the insulating cap and the active region has a lower thickness than the portion between the conductive line and the active region.

Assignees

• Xia Tai Xin Semiconductor Qing Dao Ltd

Inventors

• Kim Il-Goo

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H01L27/10814

  Electricity · mapped topic

• H01L27/10823

  Electricity · mapped topic

• H01L27/10876

  Electricity · mapped topic