Distributed processor system

Patent metadata

Field	Value
Publication number	US-11422969-B2
Application number	US-202016913251-A
Country	US
Kind code	B2
Filing date	Jun 26, 2020
Priority date	Mar 27, 2018
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

First claim

What is claimed is:

1. A method of configuring a radio with a distributed processing system that comprises a plurality of radio channels and a main processor, the method comprising:
triggering a stream in a co-processor of a radio channel of the radio channels, wherein the co-processor is in communication with the main processor, wherein the co-processor is configured to access registers of the radio channel, wherein the co-processor is configured to execute co-processor instructions, wherein the main processor is configured to execute main processor instructions, and wherein the co-processor instructions have lower latency than the main processor instructions;
executing the stream in the co-processor to at least set a value in a register of the registers of the radio channel, wherein the value in the register is configured to control a radio operation of the radio; and
providing, by the co-processor, a return in response to completing the stream.

2. The method of claim 1 , further comprising executing a second stream in a second co-processor of a second radio channel of the radio channels concurrent with executing the stream in the co-processor.

3. The method of claim 1 , wherein the triggering is in response to an input signal received by a trigger interface of the radio channel from a baseband processor that is external to the distributed processing system.

4. The method of claim 1 , wherein the main processor provides a trigger for the triggering.

5. The method of claim 1 , wherein a main co-processor provides a trigger for the triggering, and wherein the main co-processor is in communication with the main processor, the co-processor and other co-processors in other radio channels of the radio channels.

6. The method of claim 1 , further comprising providing an interrupt to the main processor via a dedicated signal line in response to the executing.

7. A stream processing system for configuring processing channels of a radio system, the stream processing system comprising:
transmit channels, wherein each of the transmit channels includes transmit registers and a transmit channel stream processor, and wherein the transmit registers are arranged to configure a transmitter of a radio for operation;
receive channels, wherein each of the receive channels includes receive registers and a receive channel stream processor, and wherein the receive registers are arranged to configure a receiver of the radio for operation;
a main stream processor configured to trigger streams in the transmit channel stream processor of each of the transmit channels and the receive channel stream processor of each of the receive channel stream processors; and
an advanced reduced instruction set computer machine (ARM) processor communicatively coupled with the main stream processor, the transmit channel stream processor of each of the transmit channels, and the receive channel stream processor of each of the receive channel stream processors.

8. The stream processing system of claim 7 , wherein each of the transmit channels comprises a stream trigger interface configured to receive an input signal from external to the stream processing system and to trigger a stream in the respective transmit channel stream processor.

9. The stream processing system of claim 7 , wherein each of the transmit channel stream processors and each of the receive channel stream processors is configured to provide an interrupt to the ARM processor.

10. The stream processing system of claim 7 , wherein the ARM processor is configured to execute higher latency instructions, and the transmit channel stream processors are configured to execute lower latency instructions that have a lower latency than the higher latency instructions.

11. The stream processing system of claim 7 , wherein the transmit channels comprise at least four transmit channels and the receive channels comprise at least four receive channels.

12. The stream processing system of claim 7 , wherein the transmit channel stream processor of each of the transmit channels includes dedicated circuitry configured to execute a timing sensitive instruction.

13. A distributed processing system for configuring processing channels of a radio, the distributed processing system comprising:
a first radio channel comprising a first co-processor and first registers, wherein the first co-processor is configured to:
execute a first stream to at least set a value in one or more of the first registers to control a first radio operation; and
provide a first return in response to completing the first stream;

a second radio channel comprising a second co-processor and second registers, wherein the second co-processor is configured to:
execute a second stream to at least set a value in at least a second register of the second registers to control a second radio operation; and
provide a second return in response to completing the second stream; and

a main processor in communication with the first co-processor and the second co-processor, the main processor configured to trigger the first stream and to trigger the second stream, wherein the main processor is configured to execute more computationally intensive instructions and the first co-processor is configured to execute less computationally intensive instructions.

14. The distributed processing system of claim 13 , wherein the second co-processor is configured to execute the second stream concurrent with the first co-processor executing the first stream.

15. The distributed processing system of claim 13 , wherein the first radio channel further comprises a trigger interface configured to receive an input signal from external to the distributed processing system.

16. The distributed processing system of claim 13 , further comprising a main co-processor in communication with the main processor, the main co-processor configured to trigger a third stream in the first co-processor and a fourth stream in the second co-processor.

17. The distributed processing system of claim 16 , wherein the main co-processor is configured to queue multiple requests for the first co-processor and the second co-processor.

18. The distributed processing system of claim 13 , wherein the first co-processor comprises dedicated circuitry configured to execute a subset of instructions of the first co-processor.

19. The distributed processing system of claim 13 , wherein the more computationally intensive instructions have a higher latency than the less computationally intensive instructions.

20. The distributed processing system of claim 13 , wherein the distributed processing system is configured to receive a high level command and write to at least one hundred registers of a plurality of radio channels in response to receiving the high level command, and wherein the plurality of radio channels comprise the first radio channel and the second radio channel.

Assignees

• Analog Devices Inc

Inventors

• Manglani Manish J
• Bhal Shipra
• Mayer Christopher

Classifications

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F9/3877 Primary

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F15/82 Primary

  data or demand driven · CPC title

• G06F9/30123

  according to context, e.g. thread buffers · CPC title