Distributed processor system

Patent metadata

Field	Value
Publication number	US-10733141-B2
Application number	US-201816103711-A
Country	US
Kind code	B2
Filing date	Aug 14, 2018
Priority date	Mar 27, 2018
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

First claim

What is claimed is:

1. A distributed processing system for configuring multiple processing channels, the distributed processing system comprising:
a main processor configured to execute main processor instructions; and
a plurality of processing channels, wherein each of the processing channels comprises:
registers configured to store data;
a co-processor configured to execute co-processor instructions that have a lower latency than the main processor instructions, and to receive a trigger from the main processor that causes the co-processor to execute a first set of instructions of the co-processor instructions, wherein the co-processor instructions include at least one instruction to access at least one of the registers; and
a trigger interface configured to receive an input signal from external to the distributed processing system and to cause the co-processor to execute a second set of instructions of the co-processor instructions in response to receiving the input signal.

2. The distributed processing system of claim 1 , further comprising a main co-processor in communication with the main processor and each of the co-processors, wherein the main co-processor is configured to trigger a stream in each of the co-processors in the processing channels.

3. The distributed processing system of claim 2 , wherein the main co-processor has access to registers of each of the processing channels.

4. The distributed processing system of claim 2 , wherein the main co-processor is in communication with the trigger interface in each of the processing channels.

5. The distributed processing system of claim 2 , wherein the main co-processor is configured to provide an interrupt to the main processor.

6. The distributed processing system of claim 2 , wherein the main co-processor is configured to queue multiple requests for the co-processors of the processing channels.

7. The distributed processing system of claim 2 , wherein the processing channels include transmit channels of a radio and receive channels of the radio, and wherein the registers in the processing channels configure the radio for operation.

8. The distributed processing system of claim 1 , wherein the distributed processing system is configured to receive a high level command and write to at least one hundred registers in the processing channels in response to receiving the high level command.

9. The distributed processing system of claim 8 , wherein the high level command is a turn on command, and the distributed processing system is configured to implement a startup process in response to receiving the turn on command.

10. The distributed processing system of claim 1 , wherein the plurality of processing channels comprises receive channels of a radio and transmit channels of the radio.

11. The distributed processing system of claim 1 , wherein each of the co-processors of the processing channels is configured to provide an interrupt to the main processor via a dedicated signal line.

12. The distributed processing system of claim 1 , wherein each of the co-processors of the processing channels is configured to execute instructions in parallel with each other.

13. The distributed processing system of claim 1 , wherein the main processor is an advanced reduced instruction set computing machine (ARM) processor and the co-processor in each processing channel is a stream processor.

14. The distributed processing system of claim 1 , wherein data in the registers in the processing channels configures analog circuit components for operation.

15. The distributed processing system of claim 14 , wherein the analog circuit components are included in a transmitter of a radio.

16. The distributed processing system of claim 1 , wherein each of the co-processors of the processing channels includes dedicated circuitry configured to execute a timing sensitive instruction of the co-processor instructions.

17. The distributed processing system of claim 1 , wherein each of the co-processors is re-configurable.

18. The distributed processing system of claim 1 , wherein the distributed processing system is implemented on a monolithic integrated circuit.

19. A method of executing instructions in a distributed processing system, the method comprising:
executing main processor instructions with a main processor;
in response to a co-processor of a processing channel receiving a trigger from the main processor, executing a first set of instructions of co-processor instructions with the co-processor, wherein the first set of instructions comprises an instruction to access at least one register of the processing channel, and wherein the co-processor instructions have lower latency than the main processor instructions;
receiving, via a trigger interface of the processing channel, an input signal from external to a distrusted processing system that includes the main processor and the processing channel; and
executing a second set of instructions of the co-processor instructions with the co-processor in response to receiving the input signal.

20. The method of claim 19 , further comprising triggering a stream in the co-processor with a main co-processor, wherein the main co-processor is in communication with the main processor and also in communication with co-processors of a plurality of processing channels, the plurality of processing channels comprising the processing channel.

21. The method of claim 20 , further comprising accessing data from registers of each of the processing channels with the main co-processor.

22. The method of claim 20 , further comprising providing an interrupt to the main processor with the main co-processor.

23. The method of claim 20 , further comprising queuing multiple requests for the co-processors of the processing channels with the main co-processor.

24. The method of claim 20 , wherein the processing channels include transmit channels of a radio and receive channels of the radio, and processing channels each comprise registers that configure the radio for operation.

25. The method of claim 20 , further comprising writing at least a hundred registers in the processing channels in response to a receiving a high level command.

26. The method of claim 25 , wherein the high level command is a turn on command, and the method comprises performing a startup process in response to receiving the turn on command.

27. The method of claim 19 , further comprising:
in response to receiving a second trigger from the main processor, executing a third set of instructions with a second co-processor of a second processing channel;
receiving, via a second trigger interface of the second processing channel, a second input signal from external to the distributed processing system; and
executing a fourth set of instructions with the second co-processor in response to receiving the second input signal.

28. The method of claim 19 , wherein the main processor is an advanced reduced instruction set computing machine (ARM) processor and the co-processor is a stream processor.

29. The method of claim 19 , wherein data in the at least one register in the processing channel configures an analog circuit component for operation.

30. The method of claim 29 , wherein the analog circuit component is included in a transmitter of a radio.

Assignees

• Analog Devices Inc

Inventors

• Manglani Manish J
• Bhal Shipra
• Mayer Christopher

Classifications

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F9/3877 Primary

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F9/30123

  according to context, e.g. thread buffers · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F15/82 Primary

  data or demand driven · CPC title